LTC2274I(RevB) View Datasheet(PDF) - Linear Technology
Part Name
Description
Manufacturer
LTC2274I Datasheet PDF : 40 Pages
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LTC2274
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER
VDD
Analog Supply Voltage
PSHDN Shutdown Power
OVDD Output Supply Range
IVDD
IOVDD
Analog Supply Current
Output Supply Current
PDIS
Power Dissipation
CONDITIONS
MIN
TYP
MAX
UNITS
l 3.135
3.3
3.465
V
SHDN Pins = VDD
5
mW
CMLOUT Directly-Coupled 50Ω to OVDD (Note 7)
l 1.2
CMLOUT Directly-Coupled 100Ω Differential (Note 7) l 1.4
CMLOUT AC-Coupled (Note 7)
l 1.4
VDD
V
VDD
V
VDD
V
DC Input
l
394
450
mA
CMLOUT Directly-Coupled, 50Ω to 0VDD
CMLOUT Directly-Coupled 100Ω Differential
CMLOUT AC-Coupled
8
mA
16
mA
16
mA
DC Input
l
1300
1485
mW
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fS
tCONV
tL
tH
tAP
tBIT, UI
tJIT
tR, tF
tSU
tHD
tCS
LATP
LATSC
LATSD
Sampling Frequency
(Note 9)
Conversion Period
ENC Clock Low Time
(Note 7)
ENC Clock High Time
(Note 7)
Sample-and-Hold Aperture Delay
Period of a Serial Bit
Total Jitter of CMLOUT± (P-P)
BER = 1E–12 (Note 7)
Differential Rise and Fall Time of CMLOUT± (20% to 80%) RTERM = 50Ω, CL = 2pF
(Note 7)
SYNC to ENC Clock Setup Time
(Note 7)
ENC Clock to SYNC Hold Time
(Note 7)
ENC Clock to SYNC Delay
(Note 7)
Pipeline Latency
Latency from SYNC Active to COMMA Out
Latency from SYNC Release to DATA Out
l
20
l 3.1
l 3.1
l
l
50
l
2
l 2.5
l
tHD
105
MHz
1/fS
s
4.762
25
ns
4.762
25
ns
0.7
ns
tCONV/20
s
0.35
UI
110
ps
ns
ns
tCONV – tSU
ns
9
Cycles
3
Cycles
2
Cycles
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND (unless otherwise
noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3.3V, fSAMPLE = 105MHz differential ENC+/ENC– = 2VP-P sine
wave with 1.6V common mode, input range = 2.25VP-P with differential
drive (PGA = 0), unless otherwise specified.
Note 5: Integral nonlinearity is defined as the deviation of a code from
a “best fit straight line” to the transfer curve. The deviation is measured
from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –1/2LSB when the
output code flickers between 0000 0000 0000 0000 and 1111 1111 1111
1111 in 2’s complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3.3V, fSAMPLE = 105MHz input range = 2.25VP-P with
differential drive.
Note 9: Recommended operating conditions.
Note 10: The dynamic current of the switched capacitors analog inputs
can be large compared to the leakage current and will vary with the sample
rate.
Note 11: Leakage current will have higher transient current at power up.
Keep drive resistance at or below 1k.
2274fb
6
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