LTC4220 View Datasheet(PDF) - Linear Technology
Part Name
Description
Manufacturer
LTC4220 Datasheet PDF : 36 Pages
| |||
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
APPLICATIONS INFORMATION
–48RTN
–48RTN
(SHORT PIN)
R1
392k
1%
R2
30.1k
1%
– 48V
*FMMT493
RIN
3× 1.8k
1/4W EACH
R4
38.3k
1 DDDINZ†13B**
CIN
1μF
VIN
9 UV
LTC4252A-1
PWRGD
2
8
OV
7
DRAIN
10
TIMER
6
GATE
CT
3
0.68μF
SS
4
VEE SENSE
C1
10nF
CSS
5
68nF
D1
BZV85C43
R5
100k
*
RD 1M
R6 27Ω
RC
10Ω
CC
10nF
**DIODES, INC
†RECOMMENDED FOR HARSH ENVIRONMENTS
Figure 19. Power Limit Circuit Breaking Application
+ CL
100μF
LOAD
EN
VOUT
Q1
IRF530S
RS
0.02Ω
425212 F19
Circuit Breaker with Foldback Current Limit
Figure 20 shows the LTC4252A in a foldback current limit
application. When VOUT is shorted to the –48V RTN supply,
current flows through resistors R4 and R5. This results in
a voltage drop across R5 and a corresponding reduction
in voltage drop across the sense resistor, RS, as the ACL
amplifier servos the sense voltage between the SENSE
and VEE pins to about 60mV. The short-circuit current
through RS reduces as the VOUT voltage increases during
an output short-circuit condition. Without foldback current
limiting resistor R5, the current is limited to 3A during
analog current limit. With R5, the short-circuit current is
limited to 0.5A when VOUT is shorted to 71V.
Inrush Control Without a Sense Resistor
During Power-Up
Figure 21 shows the LTC4252A in an application where the
inrush current is controlled without a sense resistor during
power-up. This setup is suitable only for applications that
don’t require short-circut protection from the LTC4252A.
Resistor R4 and capacitor C2 act as a feedback network
to accurately control the inrush current. The C2 capacitor
can be calculated with the following equation:
C2= IGATE •CL
IINRUSH
(19)
where IGATE = 58μA and CL is the total load capacitance.
30
Capacitor C3 and resistor R4 prevent Q1 from momen-
tarily turning on when the power pins first make contact.
Without C3 and R4, capacitor C2 pulls the gate of Q1 up
to a voltage roughly equal to VEE • C2/CGS(Q1) before the
LTC4252A powers up. By placing capacitor C3 in parallel
with the gate capacitance of Q1 and isolating them from
C2 using resistor R4, the problem is solved. The value of
C3 is given by:
( ) C3= VSUPPLY(MAX)
VGS(TH),Q1
•
C2+CGD(Q1)
(20)
C3 ≈ 35 • C2 for VSUPPLY(MAX) = 71V
where VGS(TH),Q1 is the MOSFET’s minimum gate threshold
and VSUPPLY(MAX) is the maximum operating input voltage.
Diode-ORing
Figure 22 shows the LTC4252 used as diode-oring with Hot
Swap capability in a dual – 48V power supply application.
The conventional diode-OR method uses two high power
diodes and heat sinks to contain the large heat dissipation
of the diodes. With the LTC4252 controlling the external
FETs Q2 and Q3 in a diode-OR manner, the small turn-on
voltage across the fully enhanced Q2 and Q3 reduces the
power dissipation significantly.
425212fd
Share Link: 