LTC4352CDD View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LTC4352CDD

Low Voltage Ideal Diode Controller with Monitoring

Linear Technology 

LTC4352

OPERATION

The LTC4352 controls either single or back-to-back

N-channel MOSFETs in order to emulate an ideal diode. Dual

MOSFETseliminatecurrentflow from the input to the output

in an input undervoltage or overvoltage condition.

When enabled, an amplifier (AMP) monitors the voltage

between the VIN and OUT pins, and drives the GATE pin.

The amplifier controls the gate of the external MOSFET

to servo its forward voltage drop (VIN – OUT) to 25mV.

The gate voltage rises to enhance the MOSFET if the load

current causes more than 25mV of drop. For large output

currents the MOSFET gate is driven fully on and the voltage

drop is equal to ILOAD • RDS(ON).

In the case of an input supply short-circuit, when the

MOSFET is conducting, a large reverse current starts

flowing from the load towards the input. The AMP detects

this failure condition as soon as it appears, and turns off

the MOSFET by pulling down the GATE pin. The REV pin

can be used to allow reverse current, overriding the diode

behavior.

The AMP quickly pulls-up the GATE pin whenever it senses

a large forward voltage drop. An external capacitor between

the CPO and SOURCE pins is needed for fast gate pull-up.

This capacitor is charged up, at device power-up, by the

internal charge-pump. This stored charge is used for the

fast gate pull-up.

The GATE pin sources current from the CPO pin, and sinks

current to the SOURCE and GND pins. Internal clamps

limit the GATE to SOURCE voltage to 6.1V, and the CPO

to SOURCE voltage to 6.7V. The same clamps also limit

the CPO and GATE pins to a diode voltage below the

SOURCE pin.

OV, UV, and VCC comparators, CP1 to CP3, control power

passage. The MOSFET is held off whenever the OV pin

is above 0.5V, the UV pin is below 0.5V, or the VCC pin is

below 2.57V. There is a 40μs delay from all three condi-

tions becoming good to GATE being allowed to turn on.

Overvoltage causes a fast turn-off, while undervoltage

activates a 100μA pull-down on GATE after a 7μs delay.

Open-drain pull-down, M1, pulls the STATUS pin low

when the GATE to SOURCE voltage exceeds 0.7V, to

indicate that power is passing through the MOSFET. The

FAULT output, M2, pulls low during an undervoltage or

overvoltage fault condition. It also pulls low when GATE

is fully on and the forward voltage drop exceeds 250mV,

indicating the MOSFET has too much current or has failed

open circuit.

LDO is a low dropout regulator that generates a 4.1V

supply at the VCC pin from the VIN input. When a supply

below 2.9V is being ORed, an external supply in the 2.9V

to 6V range is required at the VCC pin. Comparator CP4

will disable LDO when VIN is below VCC.

4352f

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