LTM2883 View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LTM2883

SPI/Digital or I2C µModule Isolator with Adjustable ±12.5V and 5V Regulated Power

Linear Technology 

LTM2883

Applications Information

TO

LOGIC

SIDE

GLITCH FILTER

FROM

LOGIC

SIDE

1.8mA

SDA2

2883 F11

Figure 11. Isolated SDA2 Pin Schematic

the requirements in Figures 12 and 13 for the appropri-

ate pull-up resistor on SDA that satisfies the desired rise

time specifications and VOL maximum limits for FAST and

STANDARD modes. The resistance curves represent the

maximum resistance boundary; any value may be used

to the left of the appropriate curve.

30

V = 3V

V = 3.3V

25

V = 3.6V

V = 4.5V TO 5.5V

20

15

10

5

0

10

100

1000

CBUS (pF)

2883 F12

Figure 12. Maximum Standard Speed Pull-Up Resistance on SDA

10

V = 3V

9

V = 3.3V

8

V = 3.6V

V = 4.5V TO 5.5V

7

6

5

4

3

2

1

0

10

100

1000

CBUS (pF)

2883 F13

Figure 13. Maximum Fast Speed Pull-Up Resistance on SDA

The isolated side clock pin, SCL2, has a weak push-pull

output driver; do not connect an external pull-up device.

SCL2 is compatible with I2C devices without clock stretch-

ing. On lightly loaded connections, a 100pF capacitor

from SCL2 to GND2 or RC low-pass filter (R = 500Ω C =

100pF) can be used to increase the rise and fall times and

minimize noise.

Some consideration must be given to signal coupling

between SCL2 and SDA2. Separate these signals on a

printed circuit board or route with ground between. If

these signals are wired off board, twist SCL2 with VCC2

and/or GND2 and SDA2 with GND2 and/or VCC2, do not

twist SCL2 and SDA2 together. If coupling between SCL2

and SDA2 is unavoidable, place the aforementioned RC

filter at the SCL2 pin to reduce noise injection onto SDA2.

RF, Magnetic Field Immunity

The isolator µModule technology used within the LTM2883

has been independently evaluated, and successfully passed

the RF and magnetic field immunity testing requirements

per European Standard EN 55024, in accordance with the

following test standards:

EN 61000-4-3 Radiated, Radio-Frequency,

Electromagnetic Field Immunity

EN 61000-4-8 Power Frequency Magnetic Field

Immunity

EN 61000-4-9 Pulsed Magnetic Field Immunity

Tests were performed using an unshielded test card de-

signed per the data sheet PCB layout recommendations.

Specific limits per test are detailed in Table 5.

Table 5.

TEST

EN 61000-4-3 Annex D

EN 61000-4-8 Level 4

EN 61000-4-8 Level 5

EN 61000-4-9 Level 5

*non IEC method

FREQUENCY

80MHz to 1GHz

1.4MHz to 2GHz

2GHz to 2.7GHz

50Hz and 60Hz

60Hz

Pulse

FIELD STRENGTH

10V/m

3V/m

1V/m

30A/m

100A/m*

1000A/m

2883f

22

Share Link: