M25P10-AVMP6GX View Datasheet(PDF) - Numonyx -> Micron

Part Name

Description

Manufacturer

M25P10-AVMP6GX

1 Mbit, serial Flash memory, 50 MHz SPI bus interface

Numonyx -> Micron 

M25P10-A

13 Revision history

Revision history

Table 25. Document revision history

Date

Revision

Changes

25-Feb-2001 1.0 Document written.

VFQFPN8 package (MLP8) added. Clarification of descriptions of

12-Sep-2002 1.1 entering Standby Power mode from Deep Power-down mode, and of

terminating an instruction sequence or data-out sequence.

Typical Page Program time improved. Write Protect setup and hold times

13-Dec-2002

1.2

specified, for applications that switch Write Protect to exit the Hardware

Protection mode immediately before a WRSR, and to enter the Hardware

Protection mode again immediately after.

21-Feb-2003 1.3 Erroneous address ranges corrected in memory organization table.

Table of contents, warning about exposed paddle on MLP8, and Pb-free

options added.

24-Nov-2003 2.0 40 MHz AC characteristics table included as well as 25 MHz. ICC3(max),

tSE(typ) and tBE(typ) values improved. Change of naming for VDFPN8

package.

Devices with Process technology Code X added (Read Identification

(RDID) and Table 20: AC characteristics (50 MHz operation, device grade

6)) added.

SO8 narrow package specifications updated.

08-Mar-2005 3.0 Notes 1 and 2 removed from Table 24: Ordering information scheme.

Note 1 to Table 9: Absolute maximum ratings changed, note 2 removed

and TLEAD values removed.

Small text changes. End timing line of tSHQZ modified in Figure 25: Output

timing.

01-Apr-2005

Read Identification (RDID), Deep Power-down (DP) and Release from

4.0

Deep Power-down and Read Electronic Signature (RES) instructions,

and Active Power, Standby Power and Deep Power-down modes

paragraph clarified.

01-Aug-2005

5.0

Updated Page Program (PP) instructions in Page Programming, Page

Program (PP) and Table 16: Instruction times (device grade 6).

14-Apr-2006

All packages are ECOPACK® compliant. Grade 3 information added (see

Table 10, Table 11, Table 15, Table 17, Table 18 and Table 24).

Figure 3: Bus master and memory devices on the SPI bus modified and

Note 2 added.

Table 11: Data retention and endurance added.

40MHz frequency condition modified for ICC3 in Table 14: DC

6

characteristics (device grade 6).

Table 14: DC characteristics (device grade 6) shows preliminary data.

MLP package renamed as VFQFPN and specifications updated (see

silhouette on first page, Figure 27 and Table 22). Note 2 added below

Figure 26 and Note 2 added below Figure 27. VWI parameter for device

grade 3 added to Table 8: Power-up timing and VWI threshold.

/X Process added to Table 24: Ordering information scheme.

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