M25P128
Initial delivery state
Figure 18. Power-up timing
VCC
VCC(max)
Program, Erase and Write Commands are Rejected by the Device
Chip Selection Not Allowed
VCC(min)
Reset State
of the
Device
VWI
tVSL
Read Access allowed
Device fully
accessible
tPUW
Table 8.
Symbol
Power-Up Timing and VWI Threshold
Parameter
tVSL(1)
tPUW(1)
VWI
VCC(min) to S Low
Time delay to Write instruction
Write Inhibit Voltage
1. These parameters are characterized only.
time
AI04009C
Min.
60
1
1.5
Max. Unit
µs
10 ms
2.5
V
8
Initial delivery state
The device is delivered with the memory array erased: all bits are set to 1 (each byte
contains FFh). The Status Register contains 00h (all Status Register bits are 0).
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