M25P40SVMN6TP/4 View Datasheet(PDF) - Numonyx -> Micron

Part Name

Description

Manufacturer

M25P40SVMN6TP/4

4 Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface

Numonyx -> Micron 

Revision history

13 Revision history

M25P40

Table 28. Document revision history

Date

Revision

Changes

12-Apr-2001

25-May-2001

11-Sep-2001

16-Jan-2002

12-Sep-2002

13-Dec-2002

12-Jun-2003

24-Nov-2003

12-Mar-2004

05-Aug-2004

03-Jan-2005

01-Aug-2005

24-Oct-2005

1.0 Document written.

1.1 Serial Paged Flash Memory renamed as Serial Flash Memory.

Changes to text: Signal Description/Chip Select; Hold Condition/1st para; Protection

modes; Release from Power-down and Read Electronic Signature (RES); Power-

up.

1.2

Repositioning of several tables and illustrations without changing their contents.

Power-up timing illustration; SO8W package removed.

Changes to tables: Abs Max Ratings/VIO; DC Characteristics/VIL.

FAST_READ instruction added. Document revised with new timings, VWI, ICC3 and

1.3 clock slew rate. Descriptions of Polling, Hold Condition, Page Programming,

Release for Deep Power-down made more precise. Value of tW(max) modified.

Clarification of descriptions of entering Standby Power mode from Deep Power-

1.4 down mode, and of terminating an instruction sequence or data-out sequence.

VFQFPN8 package (MLP8) added. Document promoted to Preliminary Data.

Typical Page Program time improved. Deep Power-down current changed. Write

Protect setup and hold times specified, for applications that switch Write Protect to

1.5

exit the Hardware Protection mode immediately before a WRSR, and to enter the

Hardware Protection mode again immediately after.

1.6 Document promoted from Preliminary Data to full Datasheet.

Table of contents, warning about exposed paddle on MLP8, and Pb-free options

added.

2.0

40 MHz AC Characteristics table included as well as 25 MHz. ICC3(max), tSE(typ)

and tBE(typ) values improved. Change of naming for VDFPN8 package.

Automotive range added. Soldering temperature information clarified for RoHS

3.0

compliant devices.

Device grade information clarified. Data-retention measurement temperature

4.0

corrected. Details of how to find the date of marking added.

Small text changes. Notes 2 and 3 removed from Table 27: Ordering information

5.0

scheme.

End timing line of tSHQZ modified in Figure 25: Output timing.

Updated Page Program (PP) instructions in Page Programming, Page Program

6.0

(PP), Instruction times, process technology T9HX.

50 MHz operation added (see Table 20: AC characteristics (50 MHz operation,

device grade 6, VCC min = 2.7 V)). All packages are RoHS compliant. Blank option

removed from under Plating technology in Table 27: Ordering information scheme.

7.0

MLP package renamed as VFQFPN, silhouette and package mechanical drawing

updated (see on page 1 and Figure 29: VFQFPN8 (MLP8) 8-lead Very thin Fine

pitch Quad Flat Package No lead, 6 × 5 mm, package outline.

54/57

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