M25PE80-VMN6TP View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M25PE80-VMN6TP

8 Mbit, low-voltage, Page-Erasable Serial Flash memory with byte alterability, 50 MHz SPI bus, standard pinout

STMicroelectronics 

M25PE80

Operating features

4.3

A fast way to modify data

The Page Program (PP) instruction provides a fast way of modifying data (up to 256

contiguous Bytes at a time), provided that it only involves resetting bits to 0 that had

previously been set to 1.

This might be:

● when the designer is programming the device for the first time

● when the designer knows that the page has already been erased by an earlier Page

Erase (PE), SubSector Erase (SSE), Sector Erase (SE) or Bulk Erase (BE) instruction.

This is useful, for example, when storing a fast stream of data, having first performed

the erase cycle when time was available

● when the designer knows that the only changes involve resetting bits to 0 that are still

set to 1. When this method is possible, it has the additional advantage of minimizing the

number of unnecessary erase operations, and the extra stress incurred by each page

For optimized timings, it is recommended to use the Page Program (PP) instruction to

program all consecutive targeted Bytes in a single sequence versus using several Page

Program (PP) sequences with each containing only a few Bytes (see Page Program (PP)

section and Table 21: AC characteristics).

4.4

Polling during a Write, Program or Erase cycle

A further improvement in the write, program or erase time can be achieved by not waiting for

the worst case delay (tPW, tPP, tPE, tSSE, tSE or tBE). The Write In Progress (WIP) bit is

provided in the Status Register so that the application program can monitor its value, polling

it to establish when the previous cycle is complete.

4.5

Reset

An internal Power-On Reset circuit helps protect against inadvertent data writes. Addition

protection is provided by driving Reset (RESET) Low during the Power-on process, and only

driving it High when VCC has reached the correct voltage level, VCC(min).

4.6

Active Power, Standby Power and Deep Power-Down modes

When Chip Select (S) is Low, the device is selected, and in the Active Power mode.

When Chip Select (S) is High, the device is deselected, but could remain in the Active Power

mode until all internal cycles have completed (Program, Erase, Write). The device then goes

in to the Standby Power mode. The device consumption drops to ICC1.

The Deep Power-down mode is entered when the specific instruction (the Deep Power-

down (DP) instruction) is executed. The device consumption drops further to ICC2. When in

this mode, only the Release from Deep Power-down instruction is accepted. All other

instructions are ignored. The device remains in the Deep Power-down mode until the

Release from Deep Power-down instruction is executed. This can be used as an extra

software protection mechanism, when the device is not in active use, to protect the device

from inadvertent Write, Program or Erase instructions.

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