M41T94MH6TR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M41T94MH6TR

Serial Real Time Clock with 44Bytes NVRAM and Reset

STMicroelectronics 

Operation

M41T94

3.2

Note:

READ and WRITE cycles

Address and data are shifted MSB first into the Serial Data Input (SDI) and out of the Serial

Data Output (SDO). Any data transfer considers the first bit to define whether a READ or

WRITE will occur. This is followed by seven bits defining the address to be read or written.

Data is transferred out of the SDO for a READ operation and into the SDI for a WRITE

operation. The address is always the second through the eighth bit written after the Enable

(E) pin goes low. If the first bit is a '1,' one or more WRITE cycles will occur. If the first bit is a

'0,' one or more READ cycles will occur (see Figure Figure 9 on page 17 and Figure 10 on

page 17).

Data transfers can occur one byte at a time or in multiple byte burst mode, during which the

address pointer will be automatically incremented. For a single byte transfer, one byte is

read or written and then E is driven high. For a multiple byte transfer all that is required is

that E continue to remain low. Under this condition, the address pointer will continue to

increment as stated previously. Incrementing will continue until the device is deselected by

taking E high. The address will wrap to 00h after incrementing to 3Fh.

The system-to-user transfer of clock data will be halted whenever the address being read is

a clock address (00h to 07h). Although the clock continues to maintain the correct time, this

will prevent updates of time and date during either a READ or WRITE of these address

locations by the user. The update will resume either due to a deselect condition or when the

pointer increments to an non-clock or RAM address (08h to 3Fh).

This is true both in READ and WRITE mode.

3.3

Data retention mode

With valid VCC applied, the M41T94 can be accessed as described above with READ or

WRITE cycles. Should the supply voltage decay, the M41T94 will automatically deselect,

write protecting itself when VCC falls between VPFD (max) and VPFD (min) (see Figure 17 on

page 32). At this time, the reset pin (RST) is driven active and will remain active until VCC

returns to nominal levels. When VCC falls below the switch-over voltage (VSO), power input

is switched from the VCC pin to the SNAPHAT battery (or external battery for SO16) at this

time, and the clock registers are maintained from the attached battery supply. All outputs

become high impedance. On power up, when VCC returns to a nominal value, write

protection continues for tREC by internally inhibiting E. The RST signal also remains active

during this time (see Figure 17 on page 32). Before the next active cycle, Chip Enable

should be taken high for at least tEHEL, then low.

For a further more detailed review of battery lifetime calculations, please see Application

Note AN1012.

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