M27V256-100N6TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M27V256-100N6TR Datasheet PDF : 15 Pages
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M27V256
Table 7. Read Mode DC Characteristics (1)
(TA = 0 to 70°C or –40 to 85°C; VCC = 3.3V ± 10%; VPP = VCC)
Symbol
Parameter
Test Condition
Min
Max
Unit
ILI
Input Leakage Current
0V ≤ VIN ≤ VCC
±10
µA
ILO Output Leakage Current
0V ≤ VOUT ≤ VCC
±10
µA
ICC Supply Current
E = VIL, G = VIL, IOUT = 0mA,
f = 5MHz, VCC ≤ 3.6V
10
mA
ICC1 Supply Current (Standby) TTL
E = VIH
1
mA
ICC2 Supply Current (Standby) CMOS
E > VCC – 0.2V, VCC ≤ 3.6V
10
µA
IPP Program Current
VPP = VCC
10
µA
VIL Input Low Voltage
–0.3
0.8
V
VIH (2) Input High Voltage
2
VCC + 1
V
VOL Output Low Voltage
IOL = 2.1mA
0.4
V
) Output High Voltage TTL
t(s VOH
Output High Voltage CMOS
IOH = –400µA
2.4
V
IOH = –100µA
VCC – 0.7V
V
uc Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
d 2. Maximum DC voltage on Output is VCC +0.5V.
Pro Table 8A. Read Mode AC Characteristics (1)
te (TA = 0 to 70 °C or –40 to 85°; VCC = 3.3V ± 10%; VPP = VCC)
M27V256
ole Symbol Alt
Parameter
Test Condition
-90 (3)
-100
bs Min Max Min Max
O tAVQV
tACC Address Valid to Output Valid
E = VIL, G = VIL
90
100
) - tELQV
tCE Chip Enable Low to Output Valid
G = VIL
90
100
t(s tGLQV
tOE Output Enable Low to Output Valid
E = VIL
40
45
uc tEHQZ (2) tDF Chip Enable High to Output Hi-Z
G = VIL
0
25
0
30
rod tGHQZ (2) tDF Output Enable High to Output Hi-Z
E = VIL
0
25
0
30
te P tAXQX
tOH
Address Transition to Output
Transition
E = VIL, G = VIL
0
0
le Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
o3. Speed obtained with High Speed AC measurement conditions.
Unit
ns
ns
ns
ns
ns
ns
Obs Two Line Output Control
For the most efficient use of these two control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and hat the output pins are only active when
data is desired from a particular memory device.
5/15
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