M27V256-100N6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M27V256-100N6

256 Kbit (32Kb x 8) Low Voltage UV EPROM and OTP EPROM

STMicroelectronics 

M27V256

Figure 6. Programming and Verify Modes AC Waveforms

A0-A14

Q0-Q7

tAVEL

DATA IN

VALID

DATA OUT

tQVEL

tEHQX

VPP

VCC

tVPHEL

tVCHEL

tGLQV

tGHQZ

tGHAX

E

tELEH

) G

tQXGL

uct(s PROGRAM

VERIFY

AI00759

te Prod Figure 7. Programming Flowchart

bsole VCC = 6.25V, VPP = 12.75V

- O n = 0

uct(s) NO

rod ++n

= 25

P YES

Obsolete FAIL

E = 100µs Pulse

NO

VERIFY

YES

++ Addr

Last NO

Addr

YES

PRESTO II Programming Algorithm

PRESTO II Programming Algorithm allows to pro-

gram the whole array with a guaranteed margin, in

a typical time of 3.5 seconds. Programming with

PRESTO II involves the application of a sequence

of 100µs program pulses to each byte until a cor-

rect verify occurs (see Figure 7). During program-

ming and verify operation, a MARGIN MODE

circuit is automatically activated in order to guar-

antee that each cell is programmed with enough

margin. No overprogram pulse is applied since the

verify in MARGIN MODE at VCC much higher than

3.6V provides necessary margin to each pro-

grammed cell.

Program Inhibit

Programming of multiple M27V256s in parallel

with different data is also easily accomplished. Ex-

cept for E, all like inputs including G of the parallel

M27V256 may be common. A TTL low level pulse

applied to a M27V256's E input, with VPP at 12.75

V, will program that M27V256. A high level E input

CHECK ALL BYTES

inhibits the other M27V256s from being pro-

1st: VCC = 5V

grammed.

2nd: VCC = 3V

Program Verify

AI02677

A verify (read) should be performed on the pro-

grammed bits to determine that they were correct-

ly programmed. The verify is accomplished with G

at VIL, E at VIH, VPP at 12.75V and VCC at 6.25V.

8/15

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