M28F201-120XN6TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M28F201-120XN6TR Datasheet PDF : 21 Pages
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M28F201
Table 10A. Read/Write Mode AC Characteristics, W and E Controlled
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
M28F201
Symbol Alt
Parameter
-70
VCC = 5V ± 10%
EPROM
Interface
-90
VCC = 5V ± 10%
EPROM
Interface
Unit
Min Max Min Max
tVPHEL
VPP High to Chip Enable Low
1
1
µs
tVPHWL
VPP High to Write Enable Low
1
1
µs
tWHWH3 tWC Write Cycle Time (W controlled)
70
90
ns
tEHEH3 tWC Write Cycle Time (E controlled)
70
90
ns
tAVWL
tAS Address Valid to Write Enable Low
0
0
ns
tAVEL
Address Valid to Chip Enable Low
0
0
ns
tWLAX
tAH Write Enable Low to Address Transition
30
45
ns
tELAX
Chip Enable Low to Address Transition
30
45
ns
tELWL
tCS Chip Enable Low to Write Enable Low
0
0
ns
tWLEL
Write Enable Low to Chip Enable Low
0
0
ns
tGHWL
Output Enable High to Write Enable Low
0
0
µs
tGHEL
Output Enable High to Chip Enable Low
0
0
µs
tDVWH
tDS Input Valid to Write Enable High
30
45
ns
tDVEH
Input Valid to Chip Enable High
30
45
ns
tWLWH tWP Write Enable Low to Write Enable High (Write Pulse)
30
45
ns
tELEH
Chip Enable Low to Chip Enable High (Write Pulse)
50
60
ns
tWHDX
tDH Write Enable High to Input Transition
10
10
ns
tEHDX
Chip Enable High to Input Transition
10
10
ns
tWHWH1
Duration of Program Operation (W contr.)
10
10
µs
tEHEH1
Duration of Program Operation (E contr.)
10
10
µs
tWHWH2
Duration of Erase Operation (W contr.)
9.5
9.5
ms
tEHEH2
Duration of Erase Operation (E contr.)
9.5
9.5
ms
tWHEH
tCH Write Enable High to Chip Enable High
0
0
ns
tEHWH
Chip Enable High to Write Enable High
0
0
ns
tWHWL tWPH Write Enable High to Write Enable Low
10
20
ns
tEHEL
Chip Enable High to Chip Enable Low
10
20
ns
tWHGL
Write Enable High to Output Enable Low
6
6
µs
tEHGL
Chip Enable High to Output Enable Low
6
6
µs
tAVQV
tELQX (1)
tACC Addess Valid to data Output
tLZ Chip Enable Low to Output Transition
70
90 ns
0
0
ns
tELQV
tGLQX (1)
tCE Chip Enable Low to Output Valid
tOLZ Output Enable Low to Output Transition
70
90 ns
0
0
ns
tGLQV
tEHQZ (1)
tGHQZ (1)
tOE Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
tDF Output Enable High to Output Hi-Z
25
30 ns
25
30 ns
25
30 ns
tAXQX
tOH Address Transition to Output Transition
0
0
ns
Note: 1. Sampled only, not 100% tested
10/21
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