M29DW324DT, M29DW324DB
REVISION HISTORY
Table 33. Document Revision History
Date
Version
Revision Details
19-Apr-2002
-01 Document written
08-Apr-2003
Revision numbering modified: a minor revision will be indicated by incrementing the digit
after the dot, and a major revision, by incrementing the digit before the dot (revision
version 01 equals 1.0).
Revision History moved to end of document.
When in Extended Block mode, the block at the boot block address can be used as OTP.
Data Toggle Flow chart corrected. Logic diagram corrected.
TFBGA48, 6x8mm, 0.8mm pitch package added. Identification Current IID removed from
2.0
Table 14., DC Characteristics. Erase Suspend Latency time and Data Retention
parameters and notes added to Table 7., Program, Erase Times and Program, Erase
Endurance Cycles.
APPENDIX C., EXTENDED MEMORY BLOCK, added. Auto Select Command sued to
read the Extended Memory Block. Extended Memory Block Verify Code row added to
Tables 3 and 4, Bus Operations, BYTE = VIL and Bus Operations, BYTE = VIH. Bank
Address modified in Auto Select Command. Chip Erase Address modified in Table 8.,
Status Register Bits. VSS pin connection to ground clarified. Note added to Table 22.,
Ordering Information Scheme.
Table 20., 48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data and
07-May-2003
2.1
Figure 18., 48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package
Outline” corrected.
25-Jun-2003
3.0
Document promoted from Preliminary Data to full Datasheet status. Packing option added
to Table 22., Ordering Information Scheme.
Status of Ready/Busy signal for Erase Suspend Operation modified in Table 8., Status
Register Bits.
18-Sep-2003
3.1
Figures 14 and 15, Toggle and Alternative Toggle Bits Mechanisms added.
Table 18., Toggle and Alternative Toggle Bits AC Characteristics, added.
Note 1 of Table 28., Device Geometry Definition, modified.
Figures 14 and 15, Toggle and Alternative Toggle Bits Mechanisms modified and Notes 1
07-Oct-2003
3.2
and 2 added. Table 18., Toggle and Alternative Toggle Bits AC Characteristics, modified.
Figure 8. renamed and modified; Note added.
07-Nov-2003
3.3
Block Protection Status read modified in the Auto Select command section.
VCC minimum value updated in Table 12., Operating and AC Measurement Conditions.
VPP and IPP test conditions updated in Table 14., DC Characteristics.
Architecture option updated in Table 22., Ordering Information Scheme.
Block Protect/Unprotect code updated in APPENDIX B., Table 29.
19-Dec-2003
3.4
Customer Lockable Extended Block mechanism modified in APPENDIX C., EXTENDED
MEMORY BLOCK.
APPENDIX D., BLOCK PROTECTION, updated: Note 1 added in the In-System
Technique section and Note 2 added below Figure 22., In-System Equipment Group
Protect Flowchart.
23-Mar-2004
4.0
Introduction of STATUS REGISTER section clarified.
30-Aug-2004
5.0
Section , DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE added.
TFBGA63 package removed.
10-Dec-2004
6.0
Status of Ready/Busy signal for Program Error, Chip Erase and Block Erase modified in
Table 8., Status Register Bits.
RB updated in Table 8., Status Register Bits.
14-Mar-2004
7.0
Fast Program Commands restructured and updated.
Unlock Bypass Command. updated.
48/50