M41ST85WMH6E View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M41ST85WMH6E

3.0/3.3V I²C combination serial RTC, NVRAM supervisor and microprocessor supervisor

STMicroelectronics 

Operating modes

2

Operating modes

M41ST85W

The M41ST85W clock operates as a slave device on the serial bus. Access is obtained by

implementing a start condition followed by the correct slave address (D0h). The 64 bytes

contained in the device can then be accessed sequentially in the following order:

1. Tenths/Hundredths of a Second Register

2. Seconds Register

3. Minutes Register

4. Century/Hours Register

5. Day Register

6. Date Register

7. Month Register

8. Year Register

9. Control Register

10. Watchdog Register

11 - 16. Alarm Registers

17 - 19. Reserved

20. Square Wave Register

21 - 64. User RAM

The M41ST85W clock continually monitors VCC for an out-of-tolerance condition. Should

VCC fall below VPFD, the device terminates an access in progress and resets the device

address counter. Inputs to the device will not be recognized at this time to prevent erroneous

data from being written to the device from a an out-of-tolerance system. When VCC falls

below VSO, the device automatically switches over to the battery and powers down into an

ultra low current mode of operation to conserve battery life. As system power returns and

VCC rises above VSO, the battery is disconnected, and the power supply is switched to

external VCC.

Write protection continues until VCC reaches VPFD(min) plus trec (min).

For more information on Battery Storage Life refer to Application Note AN1012.

2.1

2-wire bus characteristics

The bus is intended for communication between different ICs. It consists of two lines: a bi-

directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be

connected to a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

● Data transfer may be initiated only when the bus is not busy.

● During data transfer, the data line must remain stable whenever the clock line is High.

● Changes in the data line, while the clock line is High, will be interpreted as control

signals.

Accordingly, the following bus conditions have been defined:

12/41

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