M41T82SQA6E View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M41T82SQA6E

Serial RTC with battery switchover

STMicroelectronics 

Operation

M41T82 M41T83

2.1.5

Acknowledge

Each byte of eight bits is followed by one Acknowledge bit. This Acknowledge bit is a low

level put on the bus by the receiver whereas the master generates an extra acknowledge

related clock pulse. A slave receiver which is addressed is obliged to generate an

acknowledge after the reception of each byte that has been clocked out of the slave

transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge clock

pulse in such a way that the SDA line is a stable Low during the High period of the

acknowledge related clock pulse. Of course, setup and hold times must be taken into

account. A master receiver must signal an end of data to the slave transmitter by not

generating an acknowledge on the last byte that has been clocked out of the slave. In this

case the transmitter must leave the data line High to enable the master to generate the

STOP condition.

Figure 10. Serial bus data transfer sequence

DATA LINE

STABLE

DATA VALID

CLOCK

DATA

START

CONDITION

CHANGE OF

DATA ALLOWED

Figure 11. Acknowledgement sequence

START

SCL FROM

MASTER

1

2

DATA OUTPUT

BY TRANSMITTER

MSB

DATA OUTPUT

BY RECEIVER

STOP

CONDITION

AI00587

CLOCK PULSE FOR

ACKNOWLEDGEMENT

8

9

LSB

AI00601

16/58

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