Clock operation
M41T93
Note:
The on-chip capacitance can be calculated as follows:
CLOAD = [( AC6 – AC0 value, decimal) × 0.25pF] + 7pF
For example:
CLOAD (12h = x0000000) = 12.5pF,
CLOAD (12h =11001000) = 3.5pF, and
CLOAD (12h = 00100111) = 17.4pF.
The oscillator sees a minimum of 3.5pF with no programmable load capacitance selected.
These are typical values, and the total load capacitance seen by the crystal will include
approximately 1-2pF of package and board capacitance in addition to the Analog Calibration
register value.
Any invalid value of Analog Calibration will result in the default capacitance of 25pF.
The combination of analog and digital trimming can give up to –93 to +156 ppm of the total
adjustment.
Figure 11 on page 25 represents a typical curve of clock ppm adjustment versus the Analog
Calibration value. This curve may vary with different crystals, so it is good practice to
evaluate the crystal to be used with an M41T93 device before establishing the adjustment
values for the application in question.
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