M45PE10-VMN6P View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M45PE10-VMN6P

1 Mbit, low voltage, Page-Erasable Serial Flash memory with byte-alterability and a 50 MHz SPI bus interface

STMicroelectronics 

Instructions

M45PE10

6.4

6.4.1

6.4.2

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The

Status Register may be read at any time, even while a Program, Erase or Write cycle is in

progress. When one of these cycles is in progress, it is recommended to check the Write In

Progress (WIP) bit before sending a new instruction to the device. It is also possible to read

the Status Register continuously, as shown in Figure 9.

The status bits of the Status Register are as follows:

WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write, Program

or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is

in progress.

WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable

Latch is reset and no Write, Program or Erase instruction is accepted.

Table 5. Status Register format

b7

b0

0

0

0

0

0

0

WEL (1)

WIP(1)

1. WEL and WIP are volatile read-only bits (WEL is set and reset by specific instructions; WIP is

automatically set and reset by the internal logic of the device).

Figure 9. Read Status Register (RDSR) instruction sequence and data-out

sequence

S

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

C

Instruction

D

Status Register Out

Status Register Out

High Impedance

Q

76543210765432107

MSB

MSB

AI02031E

20/45

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