M45PE10-VMN6P View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M45PE10-VMN6P

1 Mbit, low voltage, Page-Erasable Serial Flash memory with byte-alterability and a 50 MHz SPI bus interface

STMicroelectronics 

Revision history

13 Revision history

M45PE10

Table 18. Document revision history

Date

Version

Changes

29-Apr-2003

1.0 Document written

04-Jun-2003

1.1

Description corrected of entering Hardware Protected mode (W must be

driven, and cannot be left unconnected).

04-Dec-2003

VIO(min) extended to –0.6V, tPW(typ) and tPP(typ) improved. Table of

1.2 contents, warning about exposed paddle on MLP8, and Pb-free options

added. Change of naming for VDFPN8 package.

25-Jun-2004

1.3

Soldering temperature information clarified for RoHS compliant devices.

Device Grade clarified.

22-Sep-2004

2.0 Document promoted to Preliminary Data. Minor wording changes

08-Oct-2004

3.0 Document promoted to Mature Datasheet. No other changes

4-Oct-2005

Added AC characteristics (33 MHz operation). An easy way to modify

data, A fast way to modify data, Page Write (PW) and Page Program

4.0

(PP) sections updated to explain optimal use of Page Write and Page

Program instructions. Updated ICC3 values in Table 11: DC

characteristics. Updated Table 17: Ordering information scheme. Added

ECOPACK® information.

02-Feb-2007

Document reformatted. 50 MHz frequency added (Table 14 added).

VCC supply voltage and VSS ground descriptions added.

Figure 4: SPI modes supported modified and explanatory text added.

VIO max modified in Table 7: Absolute maximum ratings.

5

At Power-up, The Write In Progress (WIP) bit is reset.

tSHQZ end timing line modified in Figure 22: Output timing.

Blank option removed below Plating technology in Table 17: Ordering

information scheme. Small text changes.

Package specifications updated (see Section 11: Package mechanical).

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