M48T58PC View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M48T58PC Datasheet PDF : 31 Pages
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Clock operations
M48T58, M48T58Y
Note:
Table 5. Register map
Data
Address
D7 D6 D5 D4 D3 D2 D1
1FFFh
10 Years
Year
1FFEh 0
0
0 10 M
Month
1FFDh BLE BL
10 Date
Date
1FFCh 0 FT CEB CB 0
Day
1FFBh 0
0
10 Hours
Hours
1FFAh 0
10 Minutes
Minutes
1FF9h ST
10 Seconds
Seconds
1FF8h W
R
S
Calibration
Function/Range
D0
BCD Format
Year
00-99
Month
01-12
Date
01-31
Century/Day 0-1/1-7
Hours
00-23
Minutes
00-59
Seconds
00-59
Control
Keys:
S = SIGN Bit
FT = FREQUENCY TEST Bit
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to '0'
BLE = Battery Low Enable Bit
BL = Battery Low Bit (Read only)
CEB = Century Enable Bit
CB = Century Bit
When CEB is set to '1,' CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century
(dependent upon the initial value set).
When CEB is set to '0,' CB will not toggle. The WRITE Bit does not need to be set to write to
CEB.
6.4
Calibrating the Clock
The M48T58/Y is driven by a quartz-controlled oscillator with a nominal frequency of 32,768
Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency
error at 25°C, which equates to about ±1.53 minutes per month. With the calibration bits
properly set, the accuracy of each M48T58/Y improves to better than +1/–2 ppm at 25°C.
The oscillation rate of any crystal changes with temperature (see Figure 8 on page 18).
Most clock chips compensate for crystal frequency and temperature shift error with
cumbersome “trim” capacitors. The M48T58/Y design, however, employs periodic counter
correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 9 on page 18. The number of times pulses
are blanked (subtracted, negative calibration) or split (added, positive calibration) depends
upon the value loaded into the five calibration bits found in the Control Register. Adding
counts speeds the clock up, subtracting counts slows the clock down.
The Calibration Byte occupies the five lower order bits (D4-D0) in the Control Register
1FF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit
16/31
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