M48T86PC1TR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M48T86PC1TR

5.0 V PC real-time clock

STMicroelectronics 

Clock operations

M48T86

3.3

Interrupts

The RTC plus RAM includes three separate, fully automatic sources of interrupt (alarm,

periodic, update-in-progress) available to a processor. The alarm interrupt can be

programmed to occur at rates from once per second to once per day. The periodic interrupt

can be selected from rates of 500 ms to 122 µs. The update-ended interrupt can be used to

indicate that an update cycle has completed.

The processor program can select which interrupts, if any, are going to be used. Three bits

in Register B enable the interrupts. Writing a logic '1' to an interrupt-enable bit (Register B;

Bit 6 = PIE; Bit 5 = AIE; Bit 4 = UIE) permits an interrupt to be initialized when the event

occurs. A '0' in an interrupt-enable bit prohibits the IRQ pin from being asserted from that

interrupt condition. If an interrupt flag is already set when an interrupt is enabled, IRQ is

immediately set at an active level, although the interrupt initiating the event may have

) occurred much earlier. As a result, there are cases where the program should clear such

t(s earlier initiated interrupts before first enabling new interrupts.

c When an interrupt event occurs, the related flag bit (Register C; Bit 6 = PF; Bit 5 = AF;

u Bit 4 = UF) is set to a logic '1.' These flag bits are set independent of the state of the

d corresponding enable bit in Register B and can be used in a polling mode without enabling

Pro t(s) the corresponding enable bits. The interrupt flag bits are status bits which software can

interrogate as necessary.

lete uc When a flag is set, an indication is given to software that an interrupt event has occurred

d since the flag bit was last read; however, care should be taken when using the flag bits as all

so ro are cleared each time Register C is read. Double latching is included with Register C so that

b P bits which are set remain stable throughout the READ cycle. All bits which are set high are

cleared when read. Any new interrupts which are pending during the READ cycle are held

- O te until after the cycle is completed. One, two, or three bits can be set when reading Register

) le C. Each utilized flag bit should be examined when read to ensure that no interrupts are lost.

t(s so The second flag bit usage method is with fully enabled interrupts. When an interrupt flag bit

c b is set and the corresponding enable bit is also set, the IRQ pin is asserted low. IRQ is

u O asserted as long as at least one of the three interrupt sources has its flag and enable bits

d - both set. The IRQF bit (Register C; Bit 7) is a '1' whenever the IRQ pin is being driven low.

ro ) Determination that the RTC initiated an interrupt is accomplished by reading Register C. A

P t(s logic '1' in the IRQF bit indicates that one or more interrupts have been initiated by the

te c M48T86. The act of reading Register C clears all active flag bits and the IRQF bit.

sole rodu 3.4

Periodic interrupt

Ob te P The periodic interrupt will cause the IRQ pin to go to an active state from once every 500 ms

leto once every 122 µs. This function is separate from the alarm interrupt which can be output

from once per second to once per day. The periodic interrupt rate is selected using the same

so Register A bits which select the square wave frequency (see Table 4 on page 18). Changing

b the Register A bits affects both the square wave frequency and the periodic interrupt output.

O However, each function has a separate enable bit in Register B. The periodic interrupt is

enabled by the PIE bit (Register B; Bit 6). The periodic interrupt can be used with software

counters to measure inputs, create output intervals, or await the next needed software

function.

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