M50FLW040AN5TP View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M50FLW040AN5TP

4-Mbit (5 × 64 Kbyte blocks + 3 × 16 × 4 Kbyte sectors) 3-V supply Firmware Hub / low-pin count Flash memory

STMicroelectronics 

M50FLW040A, M50FLW040B

Flowcharts and pseudo codes

Figure 22. Double/Quadruple Byte Program flowchart and pseudo code (FWH mode

only)

Start

Write 40h or 10h

Write Start Address

and 2/4 Data Bytes (3)

Double/Quadruple Byte Program command:

– write 40h or 10h

– write Start Address and 2/4 Data Bytes (3)

(memory enters read status state after

the Double/Quadruple Byte Program command)

Read Status

Register

NO

Suspend

NO

SR7 = 1

YES

YES

Suspend

Loop

do:

– Read Status Register

– If SR7=0 and a Program/Erase Suspend

command has been executed

– SR7 is set to 1

– Enter suspend program loop

NO

SR3 = 0

VPP Invalid

Error (1, 2)

If SR3 = 1, VPP invalid error:

– error handler

YES

NO

SR4 = 0

Program

Error (1, 2)

If SR4 = 1, Program error:

– error handler

YES

NO

SR1 = 0

YES

End

Program to Protected

Block Error (1, 2)

If SR1 = 1,

Program to protected block error:

– error handler

AI08423B

1. A Status check of SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation

by following the correct command sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. A0 and/or A1 are treated as Don’t Care (A0 for Double Byte Program and A1-A0 for Quadruple Byte

Program).

For Double Byte Program: Starting at the Start Address, the first data Byte is programmed at the even

address, and the second at the odd address.

For Quadruple Byte Program: Starting at the Start Address, the first data Byte is programmed at the

address that has A1-A0 at 00, the second at the address that has A1-A0 at 01, the third at the address that

has A1-A0 at 10, and the fourth at the address that has A1-A0 at 11.

57/64

Share Link: