M69KB096AB View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M69KB096AB

64 Mbit (4Mb x 16)/ 104MHz Clock Rate 1.8V Supply - Bare Die Burst PSRAM

STMicroelectronics 

M69KB096AB

6 Synchronous Operating modes

See Figure 27: Burst Read Interrupted by Burst Read or Write AC Waveforms and Figure 32:

Burst Write Interrupted by Burst Write or Read AC Waveforms for details on Burst Read and

Burst Write interrupt AC waveforms, respectively.

6.6 Synchronous Burst Read and Write Suspend

Synchronous Burst Read and Write operations can be suspended by halting the Clock K

holding it either High or Low. The status of the I/O signals will depend on the status of Output

enable input, G. The device internal address counter is suspended and data outputs become

high impedance tGHQZ after the rising edge of the Output Enable signal, G. It is prohibited to

suspend the first data output at the beginning of a Synchronous Burst Read.

See Figure 25 for details on the Synchronous Burst Read and Write Suspend mechanisms.

During Synchronous Burst Read and Synchronous Burst Write Suspend operations, the WAIT

output will be asserted. Bit BCR8 of the Bus Configuration Register is used to configure when

the transition of the WAIT output signal between the asserted and the de-asserted state occurs

with respect to valid data available on the data bus.

Table 4. Operating Frequency versus Latency

Latency

Mode

Configured Latency

(Clock Cycles)

Latency (Clock Cycles)

Normal

If Refresh

Collision

Variable

Latency

BCR14 = 0

(Default)

2 (3 clock cycles)

3 (4 clock cycles)

(default)

All Others

2 (3 clock cycles)

3

5

4

7

-

-

3

3 (4 clock cycles)

4

(default)

Fixed Latency 4 (5 clock cycles)

5

BCR14 = 1

5 (6 clock cycles)

6

6 (7 clock cycles)

7

All Others

-

Max Input Clock Frequency (MHz)

104 MHz

66

104

-

33

52

66

75

104

-

80 MHz

52

80

-

33

52

66

75

80

-

21/73

Share Link: