MB89530A Series
s BLOCK DIAGRAM
Sub clock
P63/INT13/X0A*1
P64/X1A*1
P60/INT10 ∼
P62/INT12
Low voltage
oscillator circuit
(32.786 kHz)
Clock control
Watch prescaler
4 External interrupt 1
(edge)
CMOS I/O port
Main clock
X0
X1
Oscillator circuit
RST
P30/PPG03/MCO
P31/SCK1 (UCK1)
/LMCO
P32/SO1 (UO1)
P33/SI1 (UI1)
P34/PTO2
P35/PWC
P36/WTO
P37/PTO1
Clock controller
Reset circuit
(watchdog timer)
21-bit time
base timer
6-bit PPF03
8-bit
PWM timer 2
8-bit
PWM timer 1
UART/SIO
PWC
CMOS I/O port
1KB RAM/2KB RAM
F2MC-8L
CPU
Wild register
32KB ROM/48KB ROM
Other pins
MOD0, MOD1, C, VCC, VSS, C/NC
CMOS I/O port
8
P00 ∼ P07
CMOS I/O port
12-bit PPG01
12-bit PPG02
CMOS I/O port
8
P10 ∼ P17
P20/PWCK
P21/PPG01
P22/PPG02
P23 ∼ P27
SIO
UART
I2C
16-bit timer/
counter 1
External interrupt 2
(level)
CMOS I/O port
N-ch output
8
10-bit
A/D converter
P40/INT20/EC
P41/INT21/SCK2
P42/INT22/
SO2/SDA
P43/INT23/
SI2/SCL
P44/INT24/UCK2
P45/INT25/UO2
P46/INT26/UI2
P47/INT27/ADST*2
8 P50/AN0 ∼
P57/AN7
AVCC
AVR
AVSS
*1 : P63/INT13, P64 pins for single-clock system and X0A, X1A pins dual-clock system
*2 : P47/INT27/ADST pins are MOD2 pin for MB89F538.
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