MB89538APFM View Datasheet(PDF) - Fujitsu
Part Name
Description
Manufacturer
MB89538APFM Datasheet PDF : 62 Pages
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MB89530A Series
(7) I2C Timing
Parameter
Start condition output
Stop condition output
Start condition detection
Stop condition detection
Restart condition output
Restart condition detection
SCL output “L” width
SCL output “H” width
SDA output delay time
Setup after SDA output
interrupt interval
SCL input “L” width
SCL input “H” width
SDA input setup
SDA input hold
(VCC = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Symbol
Pin
name
Condition
Value
Min
Max
Unit Remarks
tSTA
SCL
SDA
1 / 4 tinst ×
m × n − 20
1 / 4 tinst ×
m × n + 20
ns
Master
only
tSTO
SCL
SDA
1 / 4 tinst ×
1 / 4 tinst ×
(m × n + 8) − 20 (m × n + 8) + 20
ns
Master
only
tSTA
SCL
SDA
1 / 4 tinst × 6 + 40
ns
tSTO
SCL
SDA
1 / 4 tinst × 6 + 40
ns
tSTASU
SCL
SDA
1 / 4 tinst ×
1 / 4 tinst ×
(m × n + 8) − 20 (m × n + 8) + 20
ns
Master
only
tSTASU
SCL
SDA
1 / 4 tinst × 4 + 40
ns
tLOW
SCL
1 / 4 tinst ×
m × n − 20
1 / 4 tinst ×
m × n + 20
ns
Master
only
tHIGH
SCL
1 / 4 tinst ×
1 / 4 tinst ×
(m × n + 8) − 20 (m × n + 8) + 20
ns
Master
only
tDO
SDA
1 / 4 tinst × 4 − 20 1 / 4 tinst × 4 + 20 ns
tDOSU SDA
1 / 4 tinst × 4 − 20
ns
tLOW
SCL
1 / 4 tinst × 6 + 40
ns
tHIGH
SCL
1 / 4 tinst × 2 + 40
ns
tSU
SDA
40
ns
tHO
SDA
0
ns
Notes : • For tinst see “ (4) Instruction Cycle”.
• The value “m” in the above table is the value from the shift clock frequency setting bits (CS4-
CS3) in the clock control register “ICCR”. For details, refer to the register description in the hardware
manual.
• The value ’n’ in the above table is the value from the shift clock frequency setting bits (CS2-CS0) in the
clock control register “ICCR”. For details, refer to the register description in the hardware manual.
• tDOSU appears when the interrupt period is longer than the SCL “L” width.
• The rated values for SDA and SCL assume a start up time of 0 ns.
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