MC68HC11D0MFS1 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MC68HC11D0MFS1

ROM-based high-performance microcontrollers (MCUs)

Freescale Semiconductor 

Freescale Semiconductor, Inc.

INTERNAL

MCU CLOCK

DIVIDER

÷2 ÷4 ÷16 ÷32

S

M

MSB

LSB

M

8/16-BIT SHIFT REGISTER

S

READ DATA BUFFER

SELECT

SPI CLOCK (MASTER)

CLOCK

S

CLOCK

LOGIC

M

SPI CONTROL

MSTR

SPE

MISO

PD2

MOSI

PD3

SCK

PD4

SS

PD5

SPI STATUS REGISTER

8

8

SPI CONTROL REGISTER

8

SPI INTERRUPT

REQUEST

INTERNAL

DATA BUS

Figure 8-1 SPI Block Diagram

11 SPI BLOCK

8.2 SPI Transfer Formats

During an SPI transfer, data is simultaneously transmitted and received. A serial clock

line synchronizes shifting and sampling of the information on the two serial data lines.

A slave select line allows individual selection of a slave SPI device; slave devices that

are not selected do not interfere with SPI bus activities. On a master SPI device, the

select line can optionally be used to indicate a multiple master bus contention. Refer

to Figure 8-2.

SERIAL PERIPHERAL INTERFACE

8-2

TECHNICAL DATA

For More Information On This Product,

Go to: www.freescale.com

Share Link: