XC68HC11A8MFS4 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

XC68HC11A8MFS4

ROM-based high-performance microcontrollers

Freescale Semiconductor 

Freescale Semiconductor, Inc.

Table A-6 Expansion Bus Timing

Num

Characteristic

Symbol

1.0 MHz

2.0 MHz

3.0 MHz

Unit

Min

Max

Min

Max

Min Max

Frequency of Operation (E-Clock

Frequency)

fo

dc

1.0

dc

2.0

dc

3.0 MHz

1 Cycle Time

tcyc

1000

—

500

—

333

— ns

2 Pulse Width, E Low

PWEL = 1/2 tcyc - 23ns

PWEL

477

—

227

—

146

— ns

3 Pulse Width, E High

PWEH = 1/2 tcyc - 28 ns

PWEH

472

—

222

—

141

— ns

4A E and AS Rise Time

4B E and AS Fall Time

tr

—

20

—

20

—

20 ns

tf

—

20

—

20

—

15 ns

9 Address Hold Time

tAH = 1/8 tcyc - 29.5 ns

tAH

95.5

—

33

—

26

— ns

(Note 1a)

12 Non-Muxed Address Valid Time to E Rise tAV

281.5

—

94

—

54

— ns

tAV = PWEL - (tASD + 80 ns) (Note 1a)

17 Read Data Setup Time

tDSR

30

—

30

—

30

— ns

18 Read Data Hold Time (Max = tMAD)

tDHR

0

145.5

0

83

0

51 ns

19 Write Data Delay Time

tDDW = 1/8 tcyc + 65.5 ns

tDDW

(Note 1a)

—

190.5

—

128

—

71 ns

21 Write Data Hold Time

tDHW = 1/8 tcyc - 30 ns

tDHW

95.5

—

33

—

26

— ns

(Note 1a)

22 Muxed Address Valid Time to E Rise

tAVM

271.5

—

84

—

54

— ns

tAVM = PWEL - (tASD + 90 ns) (Note 1a)

24 Muxed Address Valid Time to AS Fall

tASL = PWASH - 70 ns

tASL

151

—

26

—

13

— ns

25 Muxed Address Hold Time

tAHL

95.5

—

33

—

31

— ns

tAHL = 1/8 tcyc - 30 ns

(Note 1b)

26 Delay Time, E to AS Rise

tASD

115.5

—

53

—

31

— ns

tASD = 1/8 tcyc - 5 ns

(Note 1a)

27 Pulse Width, AS High

PWASH = 1/4 tcyc - 30 ns

PWASH

221

—

96

—

63

— ns

28 Delay Time, AS to E Rise

tASED

115.5

—

53

—

31

— ns

tASED = 1/8 tcyc - 5 ns

(Note 1b)

29 MPU Address Access Time (Note 1a) tACCA 744.5

—

307

—

196

— ns

tACCA = tcyc – (PWEL– tAVM) – tDSR–tf

35 MPU Access Time

tACCE = PWEH - tDSR

tACCE

—

442

—

192

—

111 ns

36 Muxed Address Delay

(Previous Cycle MPU Read)

tMAD

145.5

—

83

—

51

— ns

tMAD = tASD + 30 ns(Note 1a)

NOTES:

1. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock

duty cycle are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following

expressions in place of 1/8 tcyc in the above formulas, where applicable:

(a) (1-DC) × 1/4 tcyc

(b) DC × 1/4 tcyc

Where:

DC is the decimal value of duty cycle percentage (high time).

2. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.

ELECTRICAL CHARACTERISTICS

TECHNICAL DATA

A-9

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