XC68HC11A8MFS4 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

XC68HC11A8MFS4

ROM-based high-performance microcontrollers

Freescale Semiconductor 

Freescale Semiconductor, Inc.

Table 3-2 Instruction Set (Sheet 4 of 7)

Mnemonic Operation

Description

Addressing

Instruction

Condition Codes

Mode

Opcode Operand Cycles S X H I N Z V C

INC (opr)

Increment

Memory Byte

M+1⇒M

EXT

IND,X

IND,Y 18

7C hh ll

6C ff

6C ff

6

———— ∆ ∆ ∆ —

6

7

INCA

Increment

Accumulator

A

A+1⇒A

A

INH

4C

—

2

———— ∆ ∆ ∆ —

INCB

Increment

Accumulator

B

B+1⇒B

B

INH

5C

—

2

———— ∆ ∆ ∆ —

INS

Increment

SP + 1 ⇒ SP

INH

Stack Pointer

31

—

3

————————

INX

Increment

IX + 1 ⇒ IX

INH

08

—

3

————— ∆ ——

Index Register

X

INY

Increment

IY + 1 ⇒ IY

Index Register

Y

INH

18

08

—

4

————— ∆ ——

JMP (opr)

Jump

See Figure 3–2

EXT

IND,X

IND,Y 18

7E hh ll

6E ff

6E ff

3

————————

3

4

JSR (opr)

Jump to

Subroutine

See Figure 3–2

DIR

EXT

IND,X

IND,Y 18

9D dd

BD hh ll

AD ff

AD ff

5

————————

6

6

7

LDAA (opr)

Load

Accumulator

A

M⇒A

A

IMM

86 ii

A

DIR

96 dd

A

EXT

B6 hh ll

A

IND,X

A6 ff

A

IND,Y 18

A6 ff

2

———— ∆ ∆ 0 —

3

4

4

5

LDAB (opr)

Load

Accumulator

B

M⇒B

B

IMM

C6 ii

B

DIR

D6 dd

B

EXT

F6 hh ll

B

IND,X

E6 ff

B

IND,Y 18

E6 ff

2

———— ∆ ∆ 0 —

3

4

4

5

LDD (opr)

Load Double

Accumulator

D

M ⇒ A,M + 1 ⇒ B

IMM

DIR

EXT

IND,X

IND,Y 18

CC jj kk

DC dd

FC hh ll

EC ff

EC ff

3

———— ∆ ∆ 0 —

4

5

5

6

LDS (opr)

Load Stack

Pointer

M : M + 1 ⇒ SP

IMM

DIR

EXT

IND,X

IND,Y 18

8E jj kk

9E dd

BE hh ll

AE ff

AE ff

3

———— ∆ ∆ 0 —

4

5

5

6

LDX (opr)

Load Index

Register

X

M : M + 1 ⇒ IX

IMM

DIR

EXT

IND,X

IND,Y CD

CE jj kk

DE dd

FE hh ll

EE ff

EE ff

3

———— ∆ ∆ 0 —

4

5

5

6

LDY (opr)

Load Index

Register

Y

M : M + 1 ⇒ IY

IMM 18

DIR

18

EXT 18

IND,X 1A

IND,Y 18

CE jj kk

DE dd

FE hh ll

EE ff

EE ff

4

———— ∆ ∆ 0 —

5

6

6

6

LSL (opr)

Logical Shift

Left

C b7

0

b0

EXT

IND,X

IND,Y 18

78 hh ll

68 ff

68 ff

6

———— ∆ ∆ ∆ ∆

6

7

LSLA

LSLB

Logical Shift

A

INH

Left A

C b7

0

b0

Logical Shift

B

INH

Left B

C b7

0

b0

48

—

58

—

2

———— ∆ ∆ ∆ ∆

2

———— ∆ ∆ ∆ ∆

LSLD

Logical Shift

INH

Left Double

0

C b7 A b0 b7 B b0

05

—

3

———— ∆ ∆ ∆ ∆

LSR (opr)

LSRA

Logical Shift

Right

Logical Shift

Right A

0

b7

0

b7

b0 C

A

b0 C

EXT

IND,X

IND,Y 18

INH

74 hh ll

64 ff

64 ff

44

—

6

———— 0 ∆ ∆ ∆

6

7

2

———— 0 ∆ ∆ ∆

TECHNICAL DATA

CENTRAL PROCESSING UNIT

For More Information On This Product,

Go to: www.freescale.com

3-11

Share Link: