XC68HC11A8MFS4 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

XC68HC11A8MFS4

ROM-based high-performance microcontrollers

Freescale Semiconductor 

Freescale Semiconductor, Inc.

Table 5-4 Interrupt and Reset Vector Assignments

Vector Address

Interrupt Source

CCR Mask

FFC0, C1 — FFD4, D5

FFD6, D7

FFD8, D9

FFDA, DB

FFDC, DD

FFDE, DF

FFE0, E1

FFE2, E3

FFE4, E5

FFE6, E7

FFE8, E9

FFEA, EB

FFEC, ED

FFEE, EF

FFF0, F1

FFF2, F3

FFF4, F5

FFF6, F7

FFF8, F9

FFFA, FB

FFFC, FD

FFFE, FF

Reserved

SCI Serial System

• SCI Transmit Complete

• SCI Transmit Data Register Empty

• SCI Idle Line Detect

• SCI Receiver Overrun

• SCI Receive Data Register Full

SPI Serial Transfer Complete

Pulse Accumulator Input Edge

Pulse Accumulator Overflow

Timer Overflow

Timer Input Capture 4/Output Compare 5

Timer Output Compare 4

Timer Output Compare 3

Timer Output Compare 2

Timer Output Compare 1

Timer Input Capture 3

Timer Input Capture 2

Timer Input Capture 1

Real Time Interrupt

IRQ (External Pin)

XIRQ Pin

Software Interrupt

Illegal Opcode Trap

COP Failure

Clock Monitor Fail

RESET

—

I Bit

I Bit

I Bit

I Bit

I Bit

I Bit

I Bit

I Bit

I Bit

I Bit

I Bit

I Bit

I Bit

I Bit

I Bit

X Bit

None

None

None

None

None

Local

Mask

—

—

TCIE

TIE

ILIE

RIE

RIE

SPIE

PAII

PAOVI

TOI

I4/O5I

OC4I

OC3I

OC2I

OC1I

IC3I

IC2I

IC1I

RTII

None

None

None

None

NOCOP

CME

None

5.4.1 Interrupt Recognition and Register Stacking

An interrupt can be recognized at any time after it is enabled by its local mask, if any,

and by the global mask bit in the CCR. Once an interrupt source is recognized, the

CPU responds at the completion of the instruction being executed. Interrupt latency

varies according to the number of cycles required to complete the current instruction.

When the CPU begins to service an interrupt, the contents of the CPU registers are

pushed onto the stack in the order shown in Table 5-5. After the CCR value is stacked,

the I bit and the X bit, if XIRQ is pending, are set to inhibit further interrupts. The inter-

rupt vector for the highest priority pending source is fetched, and execution continues

at the address specified by the vector. At the end of the interrupt service routine, the

return from interrupt instruction is executed and the saved registers are pulled from the

stack in reverse order so that normal program execution can resume. Refer to SEC-

TION 3 CENTRAL PROCESSING UNIT for further information.

RESETS AND INTERRUPTS

TECHNICAL DATA

5-9

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