MC908QL4ME View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MC908QL4ME

M68HC08 Microcontrollers

Freescale Semiconductor 

Computer Operating Properly (COP)

The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM)

counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after

262,128 or 8176 BUSCLKX4 cycles; depending on the state of the COP rate select bit, COPRS, in

configuration register 1. With a 262,128 BUSCLKX4 cycle overflow option, the internal 12.8-MHz

oscillator gives a COP timeout period of 20.48 ms. Writing any value to location $FFFF before an overflow

occurs prevents a COP reset by clearing the COP counter and stages 12–5 of the SIM counter.

NOTE

Service the COP immediately after reset and before entering or after exiting

stop mode to guarantee the maximum time before the first COP counter

overflow.

A COP reset pulls the RST pin low (if the RSTEN bit is set in the CONFIG1 register) for 32 × BUSCLKX4

cycles and sets the COP bit in the reset status register (RSR). See 13.8.1 SIM Reset Status Register.

NOTE

Place COP clearing instructions in the main program and not in an interrupt

subroutine. Such an interrupt subroutine could keep the COP from

generating a reset even while the main program is not working properly.

6.3 I/O Signals

The following paragraphs describe the signals shown in Figure 6-1.

6.3.1 BUSCLKX4

BUSCLKX4 is the oscillator output signal. BUSCLKX4 frequency is equal to the crystal frequency or the

RC-oscillator frequency.

6.3.2 STOP Instruction

The STOP instruction clears the SIM counter.

6.3.3 COPCTL Write

Writing any value to the COP control register (COPCTL) (see Figure 6-2) clears the COP counter and

clears stages 12–5 of the SIM counter. Reading the COP control register returns the low byte of the reset

vector.

6.3.4 Power-On Reset

The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 × BUSCLKX4 cycles after power

up.

6.3.5 Internal Reset

An internal reset clears the SIM counter and the COP counter.

6.3.6 COPD (COP Disable)

The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG).

See Chapter 5 Configuration Register (CONFIG).

MC68HC908QL4 Data Sheet, Rev. 7

68

Freescale Semiconductor

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