S9S08QD4CSC View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
S9S08QD4CSC Datasheet PDF : 198 Pages
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Analog-to-Digital Converter (S08ADC10V1)
R
W
Reset:
7
ADR7
0
6
ADR6
5
ADR5
4
ADR4
3
ADR3
2
ADR2
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-7. Data Result Low Register (ADCRL)
1
ADR1
0
0
ADR0
0
8.3.5 Compare Value High Register (ADCCVH)
This register holds the upper two bits of the 10-bit compare value. These bits are compared to the upper
two bits of the result following a conversion in 10-bit mode when the compare function is enabled.In 8-bit
operation, ADCCVH is not used during compare.
7
6
5
4
3
2
1
0
R
0
0
0
0
W
ADCV9 ADCV8
Reset:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-8. Compare Value High Register (ADCCVH)
8.3.6 Compare Value Low Register (ADCCVL)
This register holds the lower 8 bits of the 10-bit compare value, or all 8 bits of the 8-bit compare value.
Bits ADCV7:ADCV0 are compared to the lower 8 bits of the result following a conversion in either 10-bit
or 8-bit mode.
R
W
Reset:
7
ADCV7
0
6
ADCV6
5
ADCV5
4
ADCV4
3
ADCV3
2
ADCV2
1
ADCV1
0
ADCV0
0
0
0
0
0
0
0
Figure 8-9. Compare Value Low Register(ADCCVL)
8.3.7 Configuration Register (ADCCFG)
ADCCFG is used to select the mode of operation, clock source, clock divide, and configure for low power
or long sample time.
MC9S08QD4 Series MCU Data Sheet, Rev. 6
Freescale Semiconductor
103
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