S9S08QD4CSC View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

S9S08QD4CSC

8-BIT HCS08 Microcontrollers

Freescale Semiconductor 

START

FACCERR ?

1

CLEAR ERROR

Chapter 4 Memory Map and Register Definition

0

WRITE TO FCDIV(1)

0

FCBEF ?

1

WRITE TO FLASH

TO BUFFER ADDRESS AND DATA

(1) Required only once

after reset.

WRITE COMMAND TO FCMD

WRITE 1 TO FCBEF

TO LAUNCH COMMAND

AND CLEAR FCBEF (2)

(2) Wait at least four bus cycles before

checking FCBEF or FCCF.

FPVIO OR

YES

FACCERR ?

YES

NO

NEW BURST COMMAND ?

NO

ERROR EXIT

0

FCCF ?

1

DONE

Figure 4-3. Flash Burst Program Flowchart

4.5.5 Access Errors

An access error occurs whenever the command execution protocol is violated.

Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set.

FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be

processed.

• Writing to a flash address before the internal flash clock frequency has been set by writing to the

FCDIV register

• Writing to a flash address while FCBEF is not set (A new command cannot be started until the

command buffer is empty.)

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

41

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