MCP1640B-I(2015) View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

MCP1640B-I
(Rev.:2015)

0.65V Start-Up Synchronous Boost Regulator with True Output Disconnect or Input/Output Bypass Option

Microchip Technology 

MCP1640/B/C/D

5.6 Thermal Calculations

The MCP1640/B/C/D is available in two different

packages: 6-Lead SOT-23 and 8-Lead 2 x 3 DFN. The

junction temperature is estimated by calculating the

power dissipation and applying the package thermal

resistance (JA). The maximum continuous junction

temperature rating for the MCP1640/B/C/D is +125°C.

To quickly estimate the internal power dissipation for

the switching boost regulator, an empirical calculation

using measured efficiency can be used. Given the

measured efficiency, the internal power dissipation is

estimated by Equation 5-3.

EQUATION 5-3:





V----O--E---U-f--f--Ti--c---i--e--I-n--O-c---Uy-----T--

– VOUT  IOUT

=

PDis

The difference between the first term – input power,

and the second term – power delivered, is the internal

MCP1640/B/C/D power dissipation. This is an

estimate, assuming that most of the power lost is

internal to the MCP1640/B/C/D and not CIN, COUT and

the inductor. There is some percentage of power lost in

the boost inductor, with very little loss in the input and

output capacitors. For a more accurate estimation of

internal power dissipation, subtract the IINRMS2 x LESR

power dissipation.

5.7 PCB Layout Information

Good printed circuit board layout techniques are

important to any switching circuitry, and switching

power supplies are no different. When wiring the

switching high-current paths, short and wide traces

should be used. Therefore, it is important that the input

and output capacitors be placed as close as possible to

the MCP1640/B/C/D to minimize the loop area.

The feedback resistors and feedback signal should be

routed away from the switching node and the switching

current loop. When possible, ground planes and traces

should be used to help shield the feedback signal and

minimize noise and magnetic interference.

+VIN

L

Via to GND Plane

RBOT RTOP

+VOUT

CIN

MCP1640 COUT

1

GND

GND

Via for Enable

FIGURE 5-1:

MCP1640/B/C/D SOT-23-6 Recommended Layout.

 2010-2015 Microchip Technology Inc.

DS20002234D-page 17

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