MCP413X/415X/423X/425X
1.1 SPI Mode Timing Waveforms and Requirements
VIH
CS
SCK
VIHH
VIL
70
72
71
80
VIH
84
83
79
78
SDO
MSb
BIT6 - - - - - -1
LSb
75, 76
77
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
73
FIGURE 1-1:
SPI Timing Waveform (Mode = 11).
TABLE 1-1: SPI REQUIREMENTS (MODE = 11)
#
Characteristic
SCK Input Frequency
70 CS Active (VIL or VIHH) to SCK↑ input
71 SCK input high time
72 SCK input low time
73 Setup time of SDI input to SCK↑ edge
74 Hold time of SDI input from SCK↑ edge
77 CS Inactive (VIH) to SDO output hi-impedance
80 SDO data output valid after SCK↓ edge
83 CS Inactive (VIH) after SCK↑ edge
84 Hold time of CS Inactive (VIH) to
CS Active (VIL or VIHH)
Note 1: This specification by design.
Symbol
FSCK
TcsA2scH
TscH
TscL
TDIV2scH
TscH2DIL
TcsH2DOZ
TscL2DOV
TscH2csI
TcsA2csI
Min Max Units
Conditions
—
10 MHz VDD = 2.7V to 5.5V
—
1 MHz VDD = 1.8V to 2.7V
60
— ns
45
— ns VDD = 2.7V to 5.5V
500
— ns VDD = 1.8V to 2.7V
45
— ns VDD = 2.7V to 5.5V
500
— ns VDD = 1.8V to 2.7V
10
— ns
20
— ns
—
50 ns Note 1
—
70 ns VDD = 2.7V to 5.5V
170 ns VDD = 1.8V to 2.7V
100
— ns VDD = 2.7V to 5.5V
1
ms VDD = 1.8V to 2.7V
50
— ns
© 2008 Microchip Technology Inc.
DS22060B-page 11