MCP413X/415X/423X/425X
VIH
82
CS
VIHH
VIL
70
SCK
SDO
71
72
80
MSb
BIT6 - - - - - -1
LSb
VIH
84
83
75, 76
73
77
SDI
MSb IN
BIT6 - - - -1
LSb IN
FIGURE 1-2:
74
SPI Timing Waveform (Mode = 00).
TABLE 1-2: SPI REQUIREMENTS (MODE = 00)
#
Characteristic
Symbol
Min Max Units
Conditions
SCK Input Frequency
70 CS Active (VIL or VIHH) to SCK↑ input
71 SCK input high time
72 SCK input low time
73 Setup time of SDI input to SCK↑ edge
FSCK
—
—
TcsA2scH 60
TscH
45
500
TscL
45
500
TDIV2scH
10
10 MHz VDD = 2.7V to 5.5V
1 MHz VDD = 1.8V to 2.7V
— ns
— ns VDD = 2.7V to 5.5V
— ns VDD = 1.8V to 2.7V
— ns VDD = 2.7V to 5.5V
— ns VDD = 1.8V to 2.7V
— ns
74 Hold time of SDI input from SCK↑ edge
TscH2DIL
20
— ns
77 CS Inactive (VIH) to SDO output hi-impedance TcsH2DOZ
—
50 ns Note 1
80 SDO data output valid after SCK↓ edge
TscL2DOV
—
70 ns VDD = 2.7V to 5.5V
170 ns VDD = 1.8V to 2.7V
82 SDO data output valid after
TssL2doV
—
70 ns
CS Active (VIL or VIHH)
83 CS Inactive (VIH) after SCK↓ edge
TscH2csI
100
— ns VDD = 2.7V to 5.5V
1
ms VDD = 1.8V to 2.7V
84 Hold time of CS Inactive (VIH) to
CS Active (VIL or VIHH)
TcsA2csI
50
— ns
Note 1: This specification by design.
DS22060B-page 12
© 2008 Microchip Technology Inc.