MCP73861/2/3/4
3.0 PIN DESCRIPTION
The descriptions of the pins are listed in Table 3.1.
TABLE 3-1: PIN FUNCTION TABLE
MCP73861/2/3/4
QFN SOIC
Symbol
Function
1
3
2
4
3
5
4
6
5
7
6
8
7
9
8
10
9
11
10
12
11
13
12
14
13
15
14
16
15
1
16
2
17
–
VSET
VDD1
VDD2
VSS1
PROG
THREF
THERM
TIMER
VSS3
VBAT1
VBAT2
VBAT3
VSS2
EN
STAT2
STAT1
EP
Voltage Regulation Selection
Battery Management Input Supply
Battery Management Input Supply
Battery Management 0V Reference
Current Regulation Set
Cell Temperature Sensor Bias
Cell Temperature Sensor Input
Timer Set
Battery Management 0V Reference
Battery Charge Control Output
Battery Charge Control Output
Battery Voltage Sense
Battery Management 0V Reference
Logic Enable
Fault Status Output
Charge Status Output
Exposed Pad; Battery Management 0V Reference
3.1 Voltage Regulation Selection
(VSET)
MCP73861/3: Connect VSET to VSS for 4.1V regulation
voltage, connect to VDD for 4.2V regulation voltage.
MCP73862/4: Connect VSET to VSS for 8.2V regulation
voltage, connect to VDD for 8.4V regulation voltage.
3.2 Battery Management Input Supply
(VDD2, VDD1)
A supply voltage of [VREG (typ.) + 0.3V] to 12V is
recommended. Bypass to VSS with a minimum of
4.7 µF. A 1.5 kΩ resistor should be connected from
VDD to ground when using disconnectable supplies to
force VDD < VBAT when the supply is disconnected and
assure low leakage current.
3.3 Battery Management 0V Reference
(VSS1, VSS2, VSS3)
Connect to negative terminal of battery and input
supply.
3.4 Current Regulation Set (PROG)
Preconditioning, fast and termination currents are
scaled by placing a resistor from PROG to VSS.
3.5 Cell Temperature Sensor Bias
(THREF)
THREF is a voltage reference to bias external thermis-
tor for continuous cell temperature monitoring and
prequalification.
3.6 Cell Temperature Sensor Input
(THERM)
THERM is an input for an external thermistor for contin-
uous cell-temperature monitoring and prequalification.
Connect to THREF/3 to disable temperature sensing.
3.7 Timer Set
All safety timers are scaled by CTIMER/0.1 µF.
3.8 Battery Charge Control Output
(VBAT1, VBAT2)
Connect to positive terminal of battery. Drain terminal
of internal P-channel MOSFET pass transistor. Bypass
to VSS with a minimum of 4.7 µF to ensure loop stability
when the battery is disconnected.
3.9 Battery Voltage Sense (VBAT3)
VBAT3 is a voltage sense input. Connect to positive
terminal of battery. A precision internal resistor divider
regulates the final voltage on this pin to VREG.
2004-2013 Microchip Technology Inc.
DS21893F-page 13