MH8S72PHC-10 View Datasheet(PDF) - MITSUBISHI ELECTRIC
Part Name
Description
Manufacturer
MH8S72PHC-10 Datasheet PDF : 55 Pages
| |||
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72PHC -7,-8,-10
603979776-BIT (8388608 - WORD BY 72-BIT)SynchronousDRAM
OPERATION DESCRIPTION
BANK ACTIVATE
The SDRAM has four independent banks. Each bank is activated by the ACT command with
the bank address(BA0,1). A row is indicated by the row address A11-0. The minimum
activation interval between one bank and the other bank is tRRD.The number of banks which
are active concurrently is not limited.
PRECHARGE
The PRE command deactivates indicated by BA. When both banks are active, the precharge
all command(PREA,PRE + A10=H) is available to deactivate them at the same time. After tRP
from the precharge, an ACT command can be issued.
CLK
Command
A0-9
A10
A11
BA0,1
DQ
Bank Activation and Precharge All (BL=4, CL=3)
2ACT command/tRCmin
ACT
ACT READ
tRRD
Xa
Xb Y
tRCD
Xa
Xb 0
tRCmin
tRAS
Xa
Xb
PRE
tRP
1
ACT
Xb
Xb
Xb
00
01 00
01
Qa0 Qa1 Qa2 Qa3
READ
Precharge all
After tRCD from the bank activation, a READ command can be issued. 1st output date is
available after the /CAS Latency from the READ, followed by (BL-1) consecutive date when
the Burst Length is BL. The start address is specified by A8-0, and the address sequence of
burst data is defined by the Burst Type. A READ command may be applied to any active bank,
so the row precharge time(tRP) can be hidden behind continuous output data(in case of BL=8)
by interleaving the dual banks. When A10 is high at a READ command, the
auto-precharge(READA) is performed. Any command (READ, WRITE, PRE, ACT) to the
same bank is inhibited till the internal precharge is complete. The internal precharge start at
BL after READA. The next ACT command can be issued after (BL + tRP) from the previous
READA.
MIT-DS-0283-0.0
MITSUBISHI
ELECTRIC
( 18 / 55 )
9/ Dec. /1998
Share Link: 