SPC5644AF0MVZ2 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

SPC5644AF0MVZ2

Microcontroller

Freescale Semiconductor 

5 The VDDE and VDDEH supply inputs are broken into segments. Each segment of slow I/O pins (VDDEH) may have a separate supply in the 3.3

V to 5.0 V range (-10%/+5%). Each segment of fast I/O (VDDE) may have a separate supply in the 1.8 V to 3.3 V range (+/- 10%).

6 See Table 4 for details on pad types.

7 The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high impedance. Terminology is

O - output, I - input, Up - weak pull up enabled, Down - weak pull down enabled, Low - output driven low, High - output driven high. A dash for the

function in this column denotes that both the input and output buffer are turned off. The signal name to the left or right of the slash indicates the

pin is enabled.

8 Output only.

9 When used as ETRIG, this pin must be configured as an input. For GPIO it can be configured either as an input or output.

10 Maximum frequency is 50 kHz.

11 The SIU_PCR219 register is unusual in that it controls pads for two separate device pins: GPIO[219] and MCKO. See the MPC5644A

Microcontroller Reference Manual (SIU chapter) for details.

12 Multivoltage pads are automatically configured in low swing mode when a JTAG or Nexus function is selected, otherwise they are high swing.

13 On 176 LQFP and 208 MAPBGA packages, this pin is tied low internally.

14 Nexus multivoltage pads default to 5 V operation until the Nexus module is enabled.

15 EVTO should be clamped to 3.3 V to prevent possible damage to external tools that only support 3.3 V.

16 Do not connect pin directly to a power supply or ground.

17 This signal name is used to support legacy naming.

18 During and just after POR negates, internal pull resistors can be enabled, resulting in as much as 4 mA of current draw. The pull resistors are

disabled when the system clock propagates through the device.

19 For pins AN12-AN15, if the analog features are used the VDDEH7 input pins should be tied to VDDA because that segment must meet the VDDA

specification to support analog input function.

20 Do not use VRC33 to drive external circuits.

21 VDDA0 and VDDA1 are shorted together internally in BGA packages. In the QFP package the two pads are double bonded on one pin called

VDDA.

22 VSSA0 and VSSA1 are shorted together internally in BGA packages. In the QFP package the two pads are double bonded on one pin called VSSA.

23 VDDE2 and VDDE3 are shorted together in all production packages.

24 VDDE2 and VDDE3 are shorted together in all production packages.

25 VDDEH1A, VDDEH1B, and VDDEH1AB are shorted together in all production packages. The separation of the signal names is present to support

legacy naming, however they should be considered as the same signal in this document.

26 VDDEH4, VDDEH4A, VDDEH4B, and VDDEH4AB are shorted together in all production packages. The separation of the signal names is present

to support legacy naming, however they should be considered as the same signal in this document.

27 VDDEH6, VDDEH6A, VDDEH6B, and VDDEH6AB are shorted together in all production packages. The separation of the signal names is present

to support legacy naming, however they should be considered as the same signal in this document.

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