MSC7119VM1200 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MSC7119VM1200

Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

Freescale Semiconductor 

2.5.8 I2C Timing

Table 26. I2C Timing

No.

Characteristic

Fast

Unit

Min

Max

450

451

452

453

454

455

456

457

458

459

460

Note:

SCL clock frequency

0

400

kHz

Hold time START condition

(SCL clock period/2) – 0.3

—

μs

SCL low period

(SCL clock period/2) – 0.3

—

μs

SCL high period

(SCL clock period/2) – 0.1

—

μs

Repeated START set-up time (not shown in figure)

Data hold time

2 × 1/FBCK

0

—

μs

—

μs

Data set-up time

250

—

ns

SDA and SCL rise time

—

700

ns

SDA and SCL fall time

—

300

ns

Set-up time for STOP

(SCL clock period/2) – 0.7

—

μs

Bus free time between STOP and START

(SCL clock period/2) – 0.3

—

μs

SDA set-up time is referenced to the rising edge of SCL. SDA hold time is referenced to the falling edge of SCL. Load capacitance

on SDA and SCL is 400 pF.

Start Condition

453

458

457

Stop Condition Start Condition

SCL

SDA

1 23456 7 89

A

451

452

C

K

Data Byte

458

459

457

460

Start Condition

SCL

SDA

Data Byte

Figure 20. I2C Timing Diagram

MSC7119 Data Sheet, Rev. 8

36

Freescale Semiconductor

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