M48T08-150PC View Datasheet(PDF) - STMicroelectronics
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Description
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M48T08-150PC Datasheet PDF : 73 Pages
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M48T08, M48T18
CLOCK OPERATIONS (cont’d)
form. The sixth bit is a sign bit; ’1’ indicates positive
calibration, ’0’ indicates negative calibration. Cali-
bration occurs within a 64 minute cycle. The first 62
minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened
by 256 oscillator cycles. If a binary ’1’ is loaded into
the register, only the first 2 minutes in the 64 minute
cycle will be modified; if a binary 6 is loaded, the
first 12 will be affected, and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or -2.034 PPM of adjustment per calibration
step in the calibration register. Assuming that the
oscillator is in fact running at exactly 32,768 Hz,
each of the 31 increments in the Calibration byte
would represent +10.7 or - 5.35 seconds per month
which corresponds to a total range of +5.5 or - 2.75
minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T08,18 may require.
The first involves simply setting the clock, letting it
run for a month and comparing it to a known accu-
rate reference (like WWV broadcasts). While that
may seem crude, it allows the designer to give the
end user the ability to calibrate his clock as his
environment may require, even after the final prod-
uct is packaged in a non-user serviceable enclo-
sure. All the designer has to do is provide a simple
utility that accesses the Calibration byte. The utility
could even be menu driven and made foolproof.
The second approach is better suited to a manu-
facturing environment, and involves the use of
some test equipment. When the Frequency Test
(FT) bit, the seventh-most significant bit in the Day
Register, is set to a ’1’, and the oscillator is running
at 32,768 Hz, the LSB (DQ0) of the Seconds Reg-
ister will toggle at 512 Hz. Any deviation from 512
Hz indicates the degree and direction of oscillator
frequency shift at the test temperature. For exam-
ple, a reading of 512.01024 Hz would indicate a
+20 PPM oscillator frequency error, requiring a
-10(001010) to be loaded into the Calibration Byte
for correction. Note that setting or changing the
Calibration Byte does not affect the Frequency test
output frequency. The device must be selected and
addresses must stable at Address 1FF9h when
reading the 512 Hz on DQ0.
The FT bit must be set using the same method used
to set the clock, using the Write bit. The LSB of the
Seconds Register is monitored by holding the
M48T08,18 in an extended read of the Seconds
Register, without having the Read bit set. The FT
bit MUST be reset to ’0’ for normal clock operations
to resume.
Table 10. Register Map
Address
Data
D7
D6
D5
D4
D3
D2
D1
D0
1FFFh
10 Years
Year
1FFEh
0
0
0 10 M.
Month
1FFDh
0
0
10 Date
Date
1FFCh
0
FT
0
0
0
Day
1FFBh
0
0
10 Hours
Hours
1FFAh
0
10 Minutes
Minutes
1FF9h
ST
10 Seconds
Seconds
1FF8h
W
R
S
Calibration
Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit (Set to ’0’ for normal clock operation)
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to ’0’
Function/Ran ge
BCD Format
Year
Month
Date
Day
Hour
Minutes
Seconds
Control
00-99
01-12
01-31
01-07
00-23
00-59
00-59
12/18
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