AD9203-EB(Rev0) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9203-EB
(Rev.:Rev0)

10-Bit, 40 MSPS, 3 V, 74 mW A/D Converter

Analog Devices 

Figure 19 shows the reference programmed by external resistors

for 0.75 V. This will set the ADC to receive a 1.5 V span cen-

tered about 0.75 V. The reference is programmed according to

the algorithm

VREF = 0.5 V × [1 + (RA/RB)]

1.5V

0V

AINP

AINN

10␮F

VREF

0.1␮F

RA

REFSENSE

RB

ADC

CORE

+

0.5V

–

REFTF 1.875V

0.1␮F

0.1␮F

REFBF

1.125V

10␮F

0.1␮F

LOGIC

AD9203

AD9203

CLAMP OPERATION

The AD9203 contains an internal clamp. It may be used when

operating the input in a single-ended mode. The AD9203’s

clamp is very useful for clamping NTSC and PAL video signals

to ground. The clamp cannot be used in the differential input

mode.

1V p-p

REFSENSE

VREF

AD9203

AINN

CIN AINP

ADC

CORE

0Vdc

50⍀ TYP

CLAMP

IN

CLAMP

SW1

Figure 19. Programmable Reference Configuration

EXTERNAL REFERENCE OPERATION

Figure 20 illustrates the use of an external reference. An exter-

nal reference may be necessary for several reasons. Tighter

reference tolerance will enhance the accuracy of the ADC and

will allow lower temperature drift performance. When several

ADC’s track one another, a single reference (internal or exter-

nal) will be necessary. The AD9203 will draw less power when

an external reference is used.

When the REFSENSE pin is tied to AVDD, the internal refer-

ence will be disabled, allowing the use of an external reference.

The AD9203 contains an internal reference buffer. It will load

the external reference with an equivalent 10 kΩ load. The inter-

nal buffer will generate positive and negative full-scale references

for the ADC core.

In Figure 20, an external reference is used to set the midscale

set point for single-ended use. At the same time, it sets the input

voltage span through a resistor divider. If the ADC is being

driven differentially through a transformer, the external refer-

ence can set the center tap (common-mode voltage).

+5V

0.1␮F

3.0V

2.0V

1.0V

EXTERNAL

REF (2V)

10␮F

1.5k⍀ 0.1␮F

AINP

AD9203

AINN

0.1␮F

A3

VREF

1V

1.5k⍀ AVDD

REFSENSE

Figure 21. Clamp Configuration (VREF = 0.5 V)

Figure 21 shows the internal clamp circuitry and the external

control signals needed for clamp operation. To enable the clamp,

apply a logic high “1” to the CLAMP pin. This will close the

internal switch SW1. SW1 is opened by asserting the CLAMP

pin low “0.” The capacitor holds the voltage across CIN con-

stant until the next interval. The charge on the capacitor will

leak off as a function of input bias current (see Figure 22).

250

200

150

100

50

0

–50

0

0.5

1

1.5

2

2.5

3

INPUT VOLTAGE – Volts

Figure 22. Input Bias Current vs. Input Voltage

(FS = 40 MSPS)

Figure 20. External Reference Configuration

REV. 0

–11–

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