OR2T06A-3M84I View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
OR2T06A-3M84I Datasheet PDF : 192 Pages
| |||
ORCA Series 2 FPGAs
Data Sheet
June 1999
Timing Characteristics (continued)
Table 35A. OR2CxxA and OR2TxxA Asynchronous Memory Read Characteristics (MA/MB Modes)
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85°C.
Speed
Parameter
Symbol
-2
-3
-4
-5
-6
-7 Unit
Min Max Min Max Min Max Min Max Min Max Min Max
Read Operation (TJ = 85 °C, VDD = min):
Read Cycle Time
Data Valid after Address (A[3:0], B[3:0] to F[3:0])
TRC
5.1 — 3.6 — 2.7 — 2.4 — 2.3 — 2.0 — ns
MEM*_ADEL — 4.0 — 2.8 — 2.1 — 1.7 — 1.4 — 1.3 ns
Read Operation, Clocking Data into Latch/Flip-flop
(TJ = 85 °C, VDD = min):
Address to Clock Setup Time (A[3:0], B[3:0] to CK) MEM*_ASET 2.4 — 1.8 — 1.2 — 1.1 — 1.0 — 1.0 — ns
Clock to PFU Out (CK to Q[3:0])—Register
REG_DEL — 2.4 — 2.0 — 1.9 — 1.5 — 1.3 — 1.0 ns
Note: Speed grades of -5, -6, and -7 are for OR2TxxA devices only.
Table 35B. OR2TxxB Asynchronous Memory Read Characteristics (MA/MB Modes)
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Parameter
Symbol
Read Operation (TJ = 85 °C, VDD = min):
Read Cycle Time
Data Valid after Address (A[3:0], B[3:0] to F[3:0])
Read Operation, Clocking Data into Latch/Flip-flop
(TJ = 85 °C, VDD = min):
Address to Clock Setup Time (A[3:0], B[3:0] to CK)
Clock to PFU Out (CK to Q[3:0])—Register
TRC
MEM*_ADEL
MEM*_ASET
REG_DEL
Speed
-7
Min
Max
-8
Min
Max
1.9
—
1.8
—
—
1.3
—
1.0
0.9
—
0.8
—
—
1.0
—
1.0
Unit
ns
ns
ns
ns
TRC
A[3:0], B[3:0]
F[3:0]
MEM*_ADEL
Figure 55. Read Operation—Flip-Flop Bypass
5-3226(F).r4
A[3:0], B[3:0]
CK
MEM*_ASET
Q[3:0]
REG_DEL
Figure 56. Read Operation—LUT Memory Loading Flip-Flops
5-3227(F).r4
138
Lucent Technologies Inc.
Share Link: 