P89LPC932A1 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

P89LPC932A1

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM

NXP Semiconductors. 

NXP Semiconductors

P89LPC932A1

8-bit microcontroller with accelerated two-clock 80C51 core

7.17.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.

7.17.3 Mode 2

Mode 2 configures the Timer register as an 8-bit Counter with automatic reload. Mode 2

operation is the same for Timer 0 and Timer 1.

7.17.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit

counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is

in Mode 3 it can still be used by the serial port as a baud rate generator.

7.17.5 Mode 6

In this mode, the corresponding timer can be changed to a PWM with a full period of

256 timer clocks.

7.17.6 Timer overflow toggle output

Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer

overflow occurs. The same device pins that are used for the T0 and T1 count inputs are

also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first

timer overflow when this mode is turned on.

7.18 RTC/system timer

The P89LPC932A1 has a simple RTC that allows a user to continue running an accurate

timer while the rest of the device is powered-down. The RTC can be a wake-up or an

interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a

16-bit loadable down counter. When it reaches all logic 0s, the counter will be reloaded

again and the RTCF flag will be set. The clock source for this counter can be either the

CCLK or the XTAL oscillator, provided that the XTAL oscillator is not being used as the

CPU clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use CCLK as

its clock source. Only power-on reset will reset the RTC and its associated SFRs to the

default state.

P89LPC932A1_3

Product data sheet

Rev. 03 — 12 March 2007

© NXP B.V. 2007. All rights reserved.

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