M29W800AT120M6T View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M29W800AT120M6T

8 Mbit (1Mb x8 or 512Kb x16, Boot Block) Low Voltage Single Supply Flash Memory

STMicroelectronics 

M29W800AT, M29W800AB

STATUS REGISTER

P/E.C. status is indicated during execution by Data

Polling on DQ7, detection of Toggle on DQ6 and

DQ2, or Error on DQ5 and Erase Timer DQ3 bits.

Any read attempt during Program or Erase com-

mand execution will automatically output these

five Status Register bits. The P/E.C. automatically

sets bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other

bits (DQ0, DQ1 and DQ4) are reserved for future

use and should be masked. See Table 10., Status

Register Bits and Table 9., Polling and Toggle

Bits.

Data Polling Bit (DQ7). When Programming op-

erations are in progress, this bit outputs the com-

plement of the bit being programmed on DQ7.

During Erase operation, it outputs a '0'. After com-

pletion of the operation, DQ7 will output the bit last

programmed or a '1' after erasing. Data Polling is

valid and only effective during P/E.C. operation,

that is after the fourth W pulse for programming or

after the sixth W pulse for erase. It must be per-

formed at the address being programmed or at an

address within the block being erased. If all the

blocks selected for erasure are protected, DQ7 will

be set to '0' for about 100µs, and then return to the

previous addressed memory data value. See Fig-

ure 15., Data Polling Flowchart and Figure

13., Data Polling DQ7 AC Waveforms. DQ7 will

also flag the Erase Suspend mode by switching

from '0' to '1' at the start of the Erase Suspend. In

order to monitor DQ7 in the Erase Suspend mode

an address within a block being erased must be

provided. For a Read Operation in Erase Suspend

mode, DQ7 will output '1' if the read is attempted

on a block being erased and the data value on oth-

er blocks. During Program operation in Erase Sus-

pend Mode, DQ7 will have the same behavior as

in the normal program execution outside of the

suspend mode.

Toggle Bit (DQ6). When Programming or Eras-

ing operations are in progress, successive at-

tempts to read DQ6 will output complementary

data. DQ6 will toggle following toggling of either G,

or E when G is low. The operation is completed

when two successive reads yield the same output

data. The next read will output the bit last pro-

grammed or a '1' after erasing. The toggle bit DQ6

is valid only during P/E.C. operations, that is after

the fourth W pulse for programming or after the

sixth W pulse for Erase. If the blocks selected for

erasure are protected, DQ6 will toggle for about

100µs and then return back to Read. DQ6 will be

set to '1' if a Read operation is attempted on an

Erase Suspend block. When erase is suspended

DQ6 will toggle during programming operations in

a block different to the block in Erase Suspend. Ei-

ther E or G toggling will cause DQ6 to toggle. See

Figure 16., Data Toggle Flowchart and Figure

14., Data Toggle DQ6, DQ2 AC Waveforms.

Error Bit (DQ5). This bit is set to '1' by the P/E.C.

when there is a failure of programming, block

erase, or chip erase that results in invalid data in

the memory block. In case of an error in block

erase or program, the block in which the error oc-

curred or to which the programmed data belongs,

must be discarded. The DQ5 failure condition will

also appear if a user tries to program a '1' to a lo-

cation that is previously programmed to '0'. Other

Blocks may still be used. The error bit resets after

a Read/Reset (RD) instruction. In case of success

of Program or Erase, the error bit will be set to '0'.

Erase Timer Bit (DQ3). This bit is set to '0' by the

P/E.C. when the last block Erase command has

been entered to the Command Interface and it is

awaiting the Erase start. When the erase timeout

period is finished, after 50µs to 90µs, DQ3 returns

to '1'.

Toggle Bit (DQ2). This toggle bit, together with

DQ6, can be used to determine the device status

during the Erase operations. It can also be used to

identify the block being erased. During Erase or

Erase Suspend a read from a block being erased

will cause DQ2 to toggle. A read from a block not

being erased will set DQ2 to '1' during erase and

to DQ2 during Erase Suspend. During Chip Erase

a read operation will cause DQ2 to toggle as all

blocks are being erased. DQ2 will be set to '1' dur-

ing program operation and when erase is com-

plete. After erase completion and if the error bit

DQ5 is set to '1', DQ2 will toggle if the faulty block

is addressed.

Table 9. Polling and Toggle Bits

Mode

DQ7 DQ6 DQ2

Program

DQ7 Toggle 1

Erase

0 Toggle Note 1

Erase Suspend Read

(in Erase Suspend

1

1 Toggle

block)

Erase Suspend Read

(outside Erase Suspend

block)

DQ7

DQ6

DQ2

Erase Suspend Program DQ7 Toggle N/A

15/40

Share Link: