PIC16C9XX
14.3 Reset
The PIC16CXX differentiates between various kinds of
reset:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during SLEEP
• WDT Reset (normal operation)
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, and on MCLR Reset during SLEEP. They
are not affected by a WDT Wake-up, which is viewed as
the resumption of normal operation. The TO and PD
bits are set or cleared differently in different reset situ-
ations as indicated in Table 14-4. These bits are used
in software to determine the nature of the reset. See
Table 14-6 for a full description of reset states of all reg-
isters.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 14-7.
The devices all have a MCLR noise filter in the MCLR
reset path. The filter will detect and ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
FIGURE 14-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
VDD
SLEEP
WDT WDT
Module Time-out
VDD rise
detect
Power-on Reset
S
OST/PWRT
OST
10-bit Ripple counter
R
OSC1
(1) PWRT
On-chip
RC OSC
10-bit Ripple counter
Chip_Reset
Q
Enable PWRT(2)
Enable OST(2)
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2: See Table 14-3 for time-out situations.
DS30444E - page 106
© 1997 Microchip Technology Inc.