PIC16C9XX
FIGURE 14-14:INTERRUPT LOGIC
TMR1IF
TMR1IE
TMR2IF
TMR2IE
LCDIF
LCDIE
CCP1IF
CCP1IE
SSPIF
SSPIE
T0IF
T0IE
INTF
INTE
RBIF
RBIE
PEIF
PEIE
GIE
Wake-up (If in SLEEP mode)
Interrupt to CPU
ADIF
ADIE
The A/D module interrupt is implemented on the PIC16C924 only.
FIGURE 14-15:INT PIN INTERRUPT TIMING
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKOUT 3
4
INT pin
1
INTF flag
5
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst (PC)
1
Interrupt Latency 2
PC+1
Inst (PC+1)
PC+1
—
0004h
Inst (0004h)
0005h
Inst (0005h)
Instruction
executed
Inst (PC-1)
Inst (PC)
Dummy Cycle
Dummy Cycle
Inst (0004h)
Note 1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4 TCY where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF can be set anytime during the Q4-Q1 cycles.
DS30444E - page 114
© 1997 Microchip Technology Inc.