PIC16LC924-08/CL View Datasheet(PDF) - Microchip Technology
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PIC16LC924-08/CL Datasheet PDF : 189 Pages
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APPENDIX A:
The following are the list of modifications over the
PIC16C5X microcontroller family:
1. Instruction word length is increased to 14-bits.
This allows larger page sizes both in program
memory (4K now as opposed to 512 before) and
register file (192 bytes now versus 32 bytes
before).
2. A PC high latch register (PCLATH) is added to
handle program memory paging. Bits PA2, PA1,
PA0 are removed from STATUS register.
3. Data memory paging is redefined slightly. STA-
TUS register is modified.
4. Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW.
Two instructions TRIS and OPTION are being
phased out although they are kept for compati-
bility with PIC16C5X.
5. OPTION and TRIS registers are made address-
able.
6. Interrupt capability is added. Interrupt vector is
at 0004h.
7. Stack size is increased to 8 deep.
8. Reset vector is changed to 0000h.
9. Reset of all registers is revisited. Five different
reset (and wake-up) types are recognized. Reg-
isters are reset differently.
10. Wake up from SLEEP through interrupt is
added.
11. Two separate timers, Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) are
included for more reliable power-up. These tim-
ers are invoked selectively to avoid unnecessary
delays on power-up and wake-up.
12. PORTB has weak pull-ups and interrupt on
change feature.
13. T0CKI pin is also a port pin (RA4) now.
14. FSR is made a full eight bit register.
15. “In-circuit programming” is made possible. The
user can program PIC16CXX devices using only
five pins: VDD, VSS, MCLR/VPP, RB6 (clock) and
RB7 (data in/out).
16. PCON status register is added with a Power-on
Reset status bit (POR).
17. Code protection scheme is enhanced such that
portions of the program memory can be pro-
tected, while the remainder is unprotected.
PIC16C9XX
APPENDIX B: COMPATIBILITY
To convert code written for PIC16C5X to PIC16CXX,
the user should take the following steps:
1. Remove any program memory page select oper-
ations (PA2, PA1, PA0 bits) for CALL, GOTO.
2. Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits are
set properly under the new scheme.
3. Eliminate any data memory page switching.
Redefine data variables to reallocate them.
4. Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
5. Change reset vector to 0000h.
© 1997 Microchip Technology Inc.
DS30444E - page 175
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