PIC16LC924-08/CL View Datasheet(PDF) - Microchip Technology
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PIC16LC924-08/CL Datasheet PDF : 189 Pages
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4.0 MEMORY ORGANIZATION
4.1 Program Memory Organization
The PIC16C9XX family has a 13-bit program counter
capable of addressing an 8K x 14 program memory
space.
Only the first 4K x 14 (0000h-0FFFh) is physically
implemented. Accessing a location above the physi-
cally implemented addresses will cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 8
Reset Vector
0000h
Interrupt Vector
On-chip Program
Memory (Page 0)
On-chip Program
Memory (Page 1)
0004h
0005h
07FFh
0800h
0FFFh
1000h
1FFFh
PIC16C9XX
4.2 Data Memory Organization
The data memory is partitioned into four Banks which
contain the General Purpose Registers and the Special
Function Registers. Bits RP1 and RP0 are the bank
select bits.
RP1:RP0 (STATUS<6:5>)
11 = Bank 3 (180h-1FFh)
10 = Bank 2 (100h-17Fh)
01 = Bank 1 (80h-FFh)
00 = Bank 0 (00h-7Fh)
The lower locations of each Bank are reserved for the
Special Function Registers. Above the Special Func-
tion Registers are General Purpose Registers imple-
mented as static RAM. All four banks contain special
function registers. Some “high use” special function
registers are mirrored in other banks for code reduction
and quicker access.
4.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indi-
rectly through the File Select Register FSR
(Section 4.5).
The following General Purpose Registers are not phys-
ically implemented:
• F0h-FFh of Bank 1
• 170h-17Fh of Bank 2
• 1F0h-1FFh of Bank 3
These locations are used for common access across
banks.
© 1997 Microchip Technology Inc.
DS30444E - page 17
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