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PIC16C923T-08I/SP View Datasheet(PDF) - Microchip Technology

Part Name
Description
Manufacturer
PIC16C923T-08I/SP
Microchip
Microchip Technology 
PIC16C923T-08I/SP Datasheet PDF : 189 Pages
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PIC16C9XX
4.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
The special function registers can be classified into two
sets (core and peripheral). Those registers associated
with the “core” functions are described in this section,
and those related to the operation of the peripheral fea-
tures are described in the section of that peripheral fea-
ture.
TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
01h
TMR0
Timer0 module’s register
xxxx xxxx uuuu uuuu
02h
PCL
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
03h
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
04h
FSR
Indirect data memory address pointer
05h
PORTA
PORTA Data Latch when written: PORTA pins when read
xxxx xxxx uuuu uuuu
(4)
(4)
06h
PORTB PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
07h
PORTC
PORTC Data Latch when written: PORTC pins when read
--xx xxxx --uu uuuu
08h
PORTD PORTD Data Latch when written: PORTD pins when read
0000 0000 0000 0000
09h
PORTE PORTE pins when read
0000 0000 0000 0000
0Ah
PCLATH
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
0Bh
INTCON
GIE
PEIE
T0IE
0Ch
PIR1
LCDIF
ADIF(2)
INTE
RBIE
SSPIF
T0IF
CCP1IF
INTF
TMR2IF
RBIF 0000 000x 0000 000u
TMR1IF 00-- 0000 00-- 0000
0Dh
Unimplemented
0Eh
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
0Fh
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
10h
T1CON
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h
TMR2
Timer2 module’s register
0000 0000 0000 0000
12h
T2CON
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
14h
SSPCON
WCOL SSPOV SSPEN
CKP
SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h
CCPR1L Capture/Compare/PWM Register (LSB)
xxxx xxxx uuuu uuuu
16h
CCPR1H Capture/Compare/PWM Register (MSB)
xxxx xxxx uuuu uuuu
17h
CCP1CON
CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h
Unimplemented
19h
Unimplemented
1Ah
Unimplemented
1Bh
Unimplemented
1Ch
Unimplemented
1Dh
Unimplemented
1Eh(1) ADRES A/D Result Register
1Fh(1) ADCON0
ADCS1 ADCS0
CHS2
CHS1
CHS0 GO/DONE
(5)
ADON
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0',
shaded locations are unimplemented, read as ‘0’.
Note 1: Registers ADRES, ADCON0, and ADCON1 are not implemented in the PIC16C923, read as '0'.
2: These bits are reserved on the PIC16C923, always maintain these bits clear.
3: These pixels do not display, but can be used as general purpose RAM.
4: PIC16C923 reset values for PORTA: --xx xxxx for a POR, and --uu uuuu for all other resets,
PIC16C924 reset values for PORTA: --0x 0000 when read.
5: Bit1 of ADCON0 is reserved on the PIC16C924, always maintain this bit clear.
© 1997 Microchip Technology Inc.
DS30444E - page 19

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