PIC16C924-04 View Datasheet(PDF) - Microchip Technology
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Description
Manufacturer
PIC16C924-04 Datasheet PDF : 189 Pages
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7.0 TIMER0 MODULE
The Timer0 module has the following features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 7-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing bit T0CS
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
the TMR0 register is written, the increment is inhibited
for the following two instruction cycles (Figure 7-2 and
Figure 7-3). The user can work around this by writing
an adjusted value to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION<5>). In counter mode Timer0 will increment
either on every rising or falling edge of pin RA4/T0CKI.
The incrementing edge is determined by the Timer0
Source Edge Select bit T0SE (OPTION<4>). Clearing
PIC16C9XX
bit T0SE selects the rising edge. Restrictions on the
external clock input are discussed in detail in
Section 7.2.
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The pres-
caler assignment is controlled in software by control bit
PSA (OPTION<3>). Clearing bit PSA will assign the
prescaler to the Timer0 module. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4, ...,
1:256 are selectable. Section 7.3 details the operation
of the prescaler.
7.1 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt ser-
vice routine before re-enabling this interrupt. The TMR0
interrupt cannot awaken the processor from SLEEP
since the timer is shut off during SLEEP. Figure 7-4 dis-
plays the Timer0 interrupt timing.
FIGURE 7-1: TIMER0 BLOCK DIAGRAM
FOSC/4
RA4/T0CKI
pin
T0SE
0
1
T0CS
Programmable
Prescaler
3
PS2, PS1, PS0
PSout
1
0
Sync with
Internal
clocks
PSout
(2 cycle delay)
PSA
Data bus
8
TMR0
Set interrupt
flag bit T0IF
on overflow
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram).
FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
PC
(Program
Counter)
Instruction
Fetch
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
PC+6
TMR0
T0
Instruction
Executed
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
T0
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
Read TMR0
reads NT0 + 1 reads NT0 + 2
© 1997 Microchip Technology Inc.
DS30444E - page 45
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