PIC16C923T-08I/SP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16C923T-08I/SP

8-Bit CMOS Microcontroller with LCD Driver

Microchip Technology 

PIC16C9XX

10.1 Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the

16-bit value of the TMR1 register when an event occurs

on pin RC2/CCP1 (Figure 10-2). An event is defined as:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge

An event is selected by control bits CCP1M3:CCP1M0

(CCP1CON<3:0>). When a capture is made, the inter-

rupt request flag bit CCP1IF (PIR1<2>) is set. It must

be cleared in software. If another capture occurs before

the value in register CCPR1 is read, the old captured

value will be lost.

10.1.1 CCP PIN CONFIGURATION

In capture mode, the RC2/CCP1 pin should be config-

ured as an input by setting the TRISC<2> bit.

Note:

If the RC2/CCP1 pin is configured as an

output, a write to the port can cause a cap-

ture condition.

FIGURE 10-2: CAPTURE MODE OPERATION

BLOCK DIAGRAM

RC2/CCP1

pin

CCP

Prescaler

÷ 1, 4, 16

Set CCP1IF

PIR1<2>

CCPR1H

and

edge detect

Capture

Enable

TMR1H

CCP1CON<3:0>

Q’s

CCPR1L

TMR1L

10.1.2 TIMER1 MODE SELECTION

Timer1 must be running in timer mode or synchronized

counter mode for the CCP module to use the capture

feature. In asynchronous counter mode the capture

operation may not work.

10.1.3 SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep

enable bit CCP1IE (PIE1<2>) clear to avoid false inter-

rupts and should clear flag bit CCP1IF following any

such change in operating mode.

10.1.4 CCP PRESCALER

There are four prescaler settings, specified by bits

CCP1M3:CCP1M0. Whenever the CCP module is

turned off, or the CCP module is not in Capture mode,

the prescaler counter is cleared. This means that any

reset will clear the prescaler counter.

DS30444E - page 58

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared, therefore the first capture may be from

a non-zero prescaler. Example 10-1 shows the recom-

mended method for switching between capture prescal-

ers. This example also clears the prescaler counter and

will not generate the “false” interrupt.

EXAMPLE 10-1: CHANGING BETWEEN

CAPTURE PRESCALERS

CLRF

MOVLW

MOVWF

CCP1CON

; Turn CCP module off

NEW_CAPT_PS ; Load the W reg with

; the new prescaler

; mode value and CCP ON

CCP1CON

; Load CCP1CON with

; this value

10.2 Compare Mode

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the RC2/CCP1 pin is:

• Driven High

• Driven Low

• Remains Unchanged

The action on the pin is based on the value of control

bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the

same time, a compare interrupt is also generated.

FIGURE 10-3: COMPARE MODE

OPERATION BLOCK DIAGRAM

Special event trigger will reset Timer1, but not

set interrupt flag bit TMR1IF (PIR1<0>).

Set CCP1IF

PIR1<2>

CCPR1H CCPR1L

RC2/CCP1

Q S Output

Logic

R

match

TRISC<2>

Output Enable

CCP1CON<3:0>

Mode Select

Comparator

TMR1H TMR1L

10.2.1 CCP PIN CONFIGURATION

The user must configure the RC2/CCP1 pin as an out-

put by clearing the TRISC<2> bit.

Note:

Clearing the CCP1CON register will force

the RC2/CCP1 compare output latch to the

default low level. This is not the data latch.

© 1997 Microchip Technology Inc.

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